Hitachi Sh-3 Interface Timing; Figure 7-3: Hitachi Sh-3 Timing - Epson S1D13506 Technical Manual

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7.1.3 Hitachi SH-3 Interface Timing

T
CKIO
CKIO
A[20:1], M/R#
RD/WR#
BS#
CSn#
WEn#
RD#
WAIT#
D[15:0](write)
D[15:0](read)
S1D13506
X25B-A-001-12
t2 t3
t4
t6 t7
t8 t12
t9
t11
t13

Figure 7-3: Hitachi SH-3 Timing

Note
BUSCLK cannot be divided by 2 in SH-3 interface mode. MD12 must be set to 0
(BUSCLK input is not divided).
Note
The SH-3 Wait State Control Register for the area in which the S1D13506 resides must
be set to a non-zero value.
Epson Research and Development
Vancouver Design Center
t5
t17
t10
t12
t14
t15
t16
Hardware Functional Specification
Issue Date: 02/03/26