Miscellaneous Registers - Epson S1D13506 Technical Manual

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bit 0
Note

8.3.15 Miscellaneous Registers

CPU-to-Memory Access Watchdog Timer Register
REG[1F4h]
n/a n/a
bits 5-0
Hardware Functional Specification
Issue Date: 02/03/26
Memory Controller Power Save Status
This bit indicates the power save state of the memory controller.
When this bit = 1, the memory controller is powered down and is either in self refresh or
no refresh mode.
When this bit = 0, the memory controller is powered up and is either in CBR refresh or
normal mode.
When this bit reads a 1, the system may safely shut down the memory clock source.
Mem. Access Mem. Access
Watchdog Watchdog
Timer bit 5 Timer bit 4
CPU-to-Memory Access Watchdog Timer
A non-zero value in this register enables the watchdog timer for CPU-to-memory access.
When enabled, any CPU-to-memory access cycle will be completed successfully within a
time determined by the following equation:
Maximum CPU-to-memory access cycle time = (8n + 7) × T
where:
n = A non-zero value in this register
T = Bus clock period, or Bus clock period x 2 (if MD12 = 1, see
bclk
Table 5-6: on page 39)
T = Memory clock period
mclk
This function is required by some busses which time-out if the cycle duration exceeds a
certain time period. This function is not intended to arbitrarily shorten the
CPU-to-memory access cycle time in order gain higher CPU bandwidth. Doing so may
significantly reduce the available display refresh bandwidth which may cause display
corruption. This register does not affect CPU-to-register access or BitBLT access.
Mem. Access Mem. Access
Watchdog Watchdog
Timer bit 3 Timer bit 2
Page 171
RW
Mem. Access Mem. Access
Watchdog Watchdog
Timer bit 1 Timer bit 0
+ 13 × T
bclk mclk
S1D13506
X25B-A-001-12