Table 8-4: Lcd Pclk Divide Selection; Table 8-5: Lcd Pclk Source Selection - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
LCD Pixel Clock Configuration Register
REG[014h]
n/a n/a
bits 5-4
LCD PCLK Divide Select Bits
bits 1-0
LCD PCLK Source Select Bits
Note
CRT/TV Pixel Clock Configuration Register
REG[018h]
CRT/TV
PCLK 2X n/a
Enable
bit 7
Hardware Functional Specification
Issue Date: 02/03/26
LCD PCLK LCD PCLK
Divide Select Divide Select
Bit 1 Bit 0
LCD PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the LCD pixel clock from the LCD pixel
clock source.

Table 8-4: LCD PCLK Divide Selection

00
01
10
11
LCD PCLK Source Select Bits [1:0]
These bits determine the source of the LCD pixel clock for the LCD display.

Table 8-5: LCD PCLK Source Selection

00
01
10
11
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
CRT/TV CRT/TV
PCLK Divide PCLK Divide
Select Bit 1 Select Bit 0
CRT/TV PCLK 2X Enable
This bit multiplies the CRT/TV pixel clock by 2.
This bit must be set to 1 when TV with flicker filter is enabled. See REG[1FCh] bits 2-0.
n/a n/a
LCD PCLK Source to LCD PCLK Frequency Ratio
1:1
2:1
3:1
4:1
LCD PCLK Source
CLKI
BUSCLK
CLKI2
MCLK (see note)
n/a n/a
Page 129
RW
LCD PCLK LCD PCLK
Source Select Source Select
Bit 1 Bit 0
RW
CRT/TV CRT/TV
PCLK Source PCLK Source
Select Bit 1 Select Bit 0
S1D13506
X25B-A-001-12