Typical System Implementation Diagrams; Figure 3-1: Typical System Diagram (Generic Bus) - Epson S1D13506 Technical Manual

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3 Typical System Implementation Diagrams

Generic
BUS
A[27:21]
CSn#
A[20:1]
D[15:0]
WE0#
WE1#
RD0#
RD1#
WAIT#
BCLK
RESET#
Hardware Functional Specification
Issue Date: 02/03/26
For the pin mapping of each system implementation, see Table 5-7:, "CPU Interface Pin
Mapping," on page 40.
VDD
BS#
A0
M/R#
Decoder
CS#
AB[20:1]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#

Figure 3-1: Typical System Diagram (Generic Bus)

.
Oscillator Oscillator
FPDAT[7:4]
FPFRAME
S1D13506
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
4-bit
L[3:0]
Single
FPSHIFT
FPSHIFT
LCD
FPFRAME
Display
FPLINE
FPLINE
DRDY
DRDY (MOD)
GPIOx
CRT/TV
HRTC
Display
VRTC
IREF
IREF
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S1D13506
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