Fpm-Dram Cas Before Ras Refresh Timing; Table 7-18: Fpm-Dram Cas Before Ras Refresh Timing; Figure 7-18: Fpm-Dram Cas Before Ras Refresh Timing - Epson S1D13506 Technical Manual

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7.3.5 FPM-DRAM CAS Before RAS Refresh Timing

Symbol
t1
Memory clock
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
t2
RAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 00)
t3
RAS# pulse width (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
t4
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
t5
CAS# setup time
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 00)
t6
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 01 or 10)
S1D13506
X25B-A-001-12
t1
Memory
Clock
t2
RAS#
t4
CAS#

Figure 7-18: FPM-DRAM CAS Before RAS Refresh Timing

Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing

Parameter
t3
t5
t6
Min
40
2.45 t1
1.45 t1
2.45 t1 - 7
3.45 t1 - 7
1.45 t1 - 7
2.45 t1 - 7
0.45 t1 - 7
1.45 t1 - 7
2 t1
t1
0.45 t1
2.45 t1 - 4
3.45 t1 - 4
1.45 t1 - 4
2.45 t1 - 4
0.45 t1 - 4
1.45 t1 - 4
Epson Research and Development
Vancouver Design Center
Max Units
Hardware Functional Specification
Issue Date: 02/03/26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns