Table 7-25: Single Color 8-Bit Panel A.c. Timing (Format 1) - Epson S1D13506 Technical Manual

Page 92
Symbol
t1 FPFRAME setup to FPLINE falling edge
t2 FPFRAME hold from FPLINE falling edge
t3 FPLINE pulse width
t4 FPLINE period
t5a FPSHIFT2 falling edge to FPLINE rising edge, 4 bpp or 8 bpp
t5b FPSHIFT2 falling edge to FPLINE rising edge, 15/16 bpp
t6a FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
t6b FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
t7a FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 4/8 bpp
t7b FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 15/16 bpp
t8 FPSHIFT2, FPSHIFT period
t9a FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
t9b FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
t10a FPSHIFT2 falling edge to FPLINE falling edge, 4 bpp or 8 bpp
t10b FPSHIFT2 falling edge to FPLINE falling edge, 15/16 bpp
t11a FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
t11b FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
t12 FPSHIFT2, FPSHIFT pulse width high
t13 FPSHIFT2, FPSHIFT pulse width low
t14 FPDAT[7:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
t15 FPDAT[7:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1. Ts = LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
2. t1 = t4 - 12
3. t4 = [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
4. t5 = [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
5. t6 = [((REG[034h] bits [4:0]) + 1) × 8 - 29] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 15/16 bpp color depth
6. t9 = [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 15/16 bpp color depth
7. t10 = [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
S1D13506
X25B-A-001-12

Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1)

Parameter
Epson Research and Development
Vancouver Design Center
Min. Max.
Typical
Setting Setting
28 note 2 1268
12
11
40 note 3 1280
5 note 4 229
7 note 4 231
3 note 5 227
5 note 5 229
20
18
4
14 note 6 238
16 note 6 240
16 note 7 240
18 note 7 242
18
16
2
2
1
1
Hardware Functional Specification
Issue Date: 02/03/26
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts