Fpm-Dram Self-Refresh Timing; Table 7-19: Fpm-Dram Self-Refresh Timing; Figure 7-19: Fpm - Dram Self-Refresh Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center

7.3.6 FPM-DRAM Self-Refresh Timing

Memory
Clock
RAS#
CAS#
Note
Symbol
t1
Memory clock
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
t2
RAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 00)
t3
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
t4
CAS# setup time
Hardware Functional Specification
Issue Date: 02/03/26
MCLK can be stopped
(See Note)
t1
t2
t3 t4

Figure 7-19: FPM - DRAM Self-Refresh Timing

MCLK can be stopped. For timing see Section 7.4.2, "Power Save Mode" on page 79.

Table 7-19: FPM-DRAM Self-Refresh Timing

Parameter Min Max
40
2.45 t1
1.45 t1
2 t1
t1
0.45 t1
Page 77
Units
ns
ns
ns
ns
ns
ns
S1D13506
X25B-A-001-12