Multiple Function Pin Mapping; Table 5-7: Cpu Interface Pin Mapping - Epson S1D13506 Technical Manual

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5.4 Multiple Function Pin Mapping

S1D13506
Pin Generic
SH-4/SH-3
Names
AB20 A20
AB19 A19
AB18 A18
AB17 A17
AB[16:13] A[16:13] A[16:13]
AB[12:1] A[12:1]
Connected Connected to
AB0
1
to V
DD
DB[15:8] D[15:0]
DB[7:0] D[7:0]
WE1# WE1#
M/R#
CS#
BUSCLK BCLK
Connected
BS#
to V
DD
RD/WR# RD1# RD/WR#
RD# RD0#
WE0# WE0#
WAIT# WAIT#
RESET# RESET# RESET#
S1D13506
X25B-A-001-12

Table 5-7: CPU Interface Pin Mapping

Motorola
Hitachi
MIPS/ISA MC68K
Bus 1
A20 LatchA20
A19 SA19
A18 SA18
A17 SA17
SA[16:13] A[16:13]
A[12:1] SA[12:1] A[12:1]
SA0 LDS#
1
V
DD
D[15:8] SD[15:0] D[15:8]
D[7:0] SD[7:0] D[7:0]
WE1# SBHE# UDS#
External Decode
External Decode
CKIO CLK CLK
Connected to
BS#
V
DD
Connected to
R/W#
V
DD
Connected to
RD# MEMR#
Connected to
WE0# MEMW#
RDY#
IOCHRDY DTACK#
/WAIT#
inverted
RESET#
RESET
Note
All GPIO pins default to input on reset and unless programmed otherwise, must be con-
nected to either V or IO V
SS
Note
1
AB0 is not used internally for these busses and must be connected to either V
V .
DD
2
For further information on interfacing the S1D13506 to the PC Card bus, see Interfac-
ing to the PC Card Bus, document number X25B-G-005-xx.
Motorola
Motorola
MC68K
PowerPC
Bus 2
A20 A20 A11
A19 A19 A12
A18 A18 A13
A17 A17 A14
A[16:13] A[15:18]
A[12:1] A[19:30]
A0 A31
D[31:24] D[0:7]
D[23:16] D[8:15]
DS# BI
CLK CLKOUT
AS# AS# TS
R/W# RD/WR
SIZ1 TSIZ0
V
DD
SIZ0 TSIZ1
V
DD
DSACK1# TA
RESET# RESET#
if not used.
DD
Epson Research and Development
Vancouver Design Center
Philips
PC Card PR31500
/PR31700
A20 ALE
A19 /CARDREG
A18 /CARDIORD
A17 /CARDIOWR
A[16:13]
Connected to V
DD
A[12:1] A[12:1]
Connected to
A0
1
V
DD
D[15:0] D[23:16]
D[7:0] D[31:24]
CE2# /CARDxCSH
Connected to V
DD
Connected to V
DD
External
DCLKOUT
2
Oscillator
Connected to
Connected to V
DD
V
DD
CE1# /CARDxCSL
OE# /RD
WE# /WE
WAIT# /CARDxWAIT CARDxWAIT*
inverted
RESET#
RESET
Hardware Functional Specification
Issue Date: 02/03/26
Toshiba
TX3912
ALE
CARDREG*
CARDIORD*
CARDIOWR*
Connected to V
DD
A[12:1]
A0
D[23:16]
D[31:24]
CARDxCSH*
Connected to V
DD
Connected to V
DD
DCLKOUT
Connected to V
DD
CARDxCSL*
RD*
WE*
PON*
or
SS