Table 7-6: Motorola Mc68030 Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Clock frequency
CLK
T Clock period
CLK
t2 Clock pulse width high
t3 Clock pulse width low
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0,
t4
AS# = 0, and DS# = 0
t5 A[20:0], SIZ[1:0], M/R# hold from AS#
t6 CS# hold from AS#
t7 R/W# setup to DS#
t8 R/W# hold from AS#
t9 AS# = 0 and CS# = 0 to DSACK1# driven high
t10 AS# high to DSACK1# high
t11 First BCLK where AS# = 1 to DSACK1# high impedance
D[31:16] valid to third CLK where CS# = 0, AS# = 0, and
t12
DS# = 0 (write cycle)
t13 D[31:16] hold from falling edge of DSACK1# (write cycle)
t14 Falling edge of DS# = 0 to D[31:16] driven (read cycle)
t15 D[31:16] valid to DSACK1# falling edge (read cycle)
t16 DS# high to D[31:16] invalid/high impedance (read cycle)
t17 AS# high setup to CLK
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-6: Motorola MC68030 Timing

Parameter
3.0V 5.0V
Min Max Min
50
1/f 1/f
CLK CLK
6 6
6 6
5 3
0 0
0 0
10 10
0 0
1 1
4 18 3
3 15 2
0 0
0 0
3 3
0 0
6 31 4
4 3
Page 59
Max Units
50 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 ns
14 ns
ns
ns
ns
ns
15 ns
ns
S1D13506
X25B-A-001-12