Table 7-26: Single Color 8-Bit Panel A.c. Timing (Format 2) - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
t1 FPFRAME setup to FPLINE falling edge
t2 FPFRAME hold from FPLINE falling edge
t3 FPLINE pulse width
t4 FPLINE period
t5 DRDY (MOD) delay from FPLINE falling edge
t6a FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
t6b FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
t7a FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
t7b FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
t8 FPSHIFT period
t9a FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
t9b FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
t10a FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
t10b FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
t11 FPSHIFT pulse width high
t12 FPSHIFT pulse width low
t13 FPDAT[7:0] setup to FPSHIFT falling edge
t14 FPDAT[7:0] hold to FPSHIFT falling edge
1. Ts = LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
2. t1 = t4 - 12
3. t4 = [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
4. t5 = [((REG[034h] bits [4:0]) + 1) × 8 + 3]
5. t6 = [((REG[034h] bits [4:0]) + 1) × 8 - 28] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 26] for 15/16 bpp color depth
6. t9 = [((REG[034h] bits [4:0]) + 1) × 8 - 17] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 15] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2)

Parameter
Min. Max.
Typical
Setting Setting
28 note 2 1268
12
11
40 note 3 1280
3 note 4
4 note 5 228
6 note 5 230
20
18
2
15 note 6 239
17 note 6
18
16
1
1
1
1
Page 95
Units
Ts (note 1)
Ts
Ts
Ts
259 Ts
Ts
Ts
Ts
Ts
Ts
Ts
241 Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13506
X25B-A-001-12