Single Color 8-Bit Panel Timing (Format 1); Figure 7-28: Single Color 8-Bit Panel Timing (Format 1) - Epson S1D13506 Technical Manual

Page 90

7.5.4 Single Color 8-Bit Panel Timing (Format 1)

FPFRAME
FPLINE
FPDAT[7:0]
FPLINE
FPSHIFT
FPSHIFT2
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13506
X25B-A-001-12
LINE1 LINE2 LINE3
1-R1 1-G1 1-G6 1-B6
1-B1 1-R2 1-R7 1-G7
1-G2 1-B2 1-B7 1-R8
1-R3 1-G3 1-G8 1-B8
1-B3 1-R4 1-R9 1-G9
1-G4 1-B4 1-B9 1-R10
1-R5 1-G5 1-G10 1-B10
1-B5 1-R6 1-R11 1-G11

Figure 7-28: Single Color 8-Bit Panel Timing (Format 1)

= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
VDP
LINE4
LINE479 LINE480
HDP
1-B11 1-R12
1-G12 1-B12
1-R13 1-G13
1-B13 1-R14
1-G14 1-B14
1-R15 1-G15
1-B15 1-R16
1-G16 1-B16
Epson Research and Development
Vancouver Design Center
VNDP
LINE1 LINE2
HNDP
1-R636
1-B636
1-G637
1-R638
1-B638
1-G639
1-R640
1-B640
Hardware Functional Specification
Issue Date: 02/03/26