Bandwidth Limitation - Epson S1D13506 Technical Manual

Page 210

16.2 Bandwidth Limitation

S1D13506
X25B-A-001-12
When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth
available to the S1D13506. The result is that display modes with a high resolution or color
depth may not be supported. In some cases, Ink Layers may not be possible on one or both
of the displays. EISD increases the total demand for display refresh bandwidth and reduces
CPU bandwidth, resulting in lower CPU performance.
In a few cases when EISD is enabled, the default LCD and CRT/TV Display FIFO High
Threshold Control register values are not optimally set, causing display problems with one
or both of the displays. This condition may be corrected by adjusting the values of the LCD
and CRT/TV Display FIFO High Threshold Control registers (REG[04Ah] for LCD and
REG[06Ah] for CRT/TV).
When the FIFO High Threshold Control register is set to 00h (default), the following
settings are used:
• 11h for 4 bpp mode
• 21h for 8 bpp mode
• 23h for 15/16 bpp mode
Changing this register to a non-zero value sets the high threshold FIFO level to this value.
This register may not exceed 59 decimal. The high threshold FIFO level controls how often
display fetch requests are issued by the FIFO. In general, a higher high threshold FIFO level
increases the bandwidth to that display pipe, and a lower level reduces it.
Most display problems may be corrected by increasing the associated high threshold FIFO
level for that display. However, because the total available bandwidth is fixed, this change
may create display problem for the other display. In this case, reducing the high threshold
FIFO level for the other display instead may work. Sometimes, a combination of these two
methods is required. Correcting EISD display problems by adjusting the FIFO High
Threshold Control registers is mostly a trial-and-error process. While the user is free to
experiment with these registers, recommended FIFO level settings for some of the more
common EISD modes requiring non-default FIFO level settings are listed in Section 18.2,
"Example Frame Rates" on page 215.
Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 02/03/26