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Epson S1D13504 Technical Manual

Color graphics lcd/crt controller
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Table of Contents
S1D13504 Color Graphics LCD/CRT Controller
S1D13504
TECHNICAL MANUAL
Document Number: X19A-Q-002-14
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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  • Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 TECHNICAL MANUAL X19A-Q-002-14 Issue Date: 01/04/18...
  • Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics.
  • Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 TECHNICAL MANUAL X19A-Q-002-14 Issue Date: 01/04/18...
  • Page 5 February 2001 DESCRIPTION The S1D13504 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system.
  • Page 6 Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
  • Page 7 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 8 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 9: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ..........11 Scope .
  • Page 10 Page 4 Epson Research and Development Vancouver Design Center 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) ......38 7.1.3...
  • Page 11 Epson Research and Development Page 5 Vancouver Design Center 8.2.9 External RAMDAC Control Registers ......112 Display Buffer .
  • Page 12 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 13 S1D13504 Series Package list ........
  • Page 14 S1D13504 Addressing ........
  • Page 15 Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM ....14 Figure 3-2: Typical System Diagram –...
  • Page 16 Page 10 Epson Research and Development Vancouver Design Center Figure 7-33: Dual Color 8-Bit Panel Timing ........79 Figure 7-34: Dual Color 8-Bit Panel A.C.
  • Page 17: Introduction

    The S1D13504 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system.
  • Page 18: Features

    Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Memory Interface • 16-bit DRAM interface: • EDO-DRAM up to 40MHz data rate (80M bytes per second). • FPM-DRAM up to 25MHz data rate (50M bytes per second).
  • Page 19: Display Modes

    • The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight – its power-on polarity is selected by an MD configuration pin. 2.7 Package and Pin Table 2-1: S1D13504 Series Package list Name Package S1D13504F00A...
  • Page 20: Typical System Implementation Diagrams

    Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Power Oscillator Management SH-3 M/R# CSn# A[20:0] AB[20:0] FPDAT[15:8] UD[7:0] D[15:0] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT WE1# WE1# S1D13504 FPFRAME FPFRAME Display RD/WR# RD/WR# FPLINE...
  • Page 21: Figure 3-2: Typical System Diagram - Mc68K Bus 1, 1Mx16 Fpm/Edo-Dram (16-Bit Mc68000)

    Epson Research and Development Page 15 Vancouver Design Center Power Oscillator Management MC68000 A[23:21] M/R# Decoder FC0, FC1 Decoder A[20:1] AB[20:1] FPDAT[15:8] UD[7:0] D[15:0] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT S1D13504 LDS# AB0# Display FPFRAME FPFRAME UDS# WE1# FPLINE FPLINE...
  • Page 22: Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 Fpm/Edo-Dram

    Page 16 Epson Research and Development Vancouver Design Center Power Oscillator Management GENERIC M/R# CSn# A[20:0] AB[20:0] FPDAT[15:8] UD[7:0] D[15:0] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT S1D13504 WE0# WE0# Display FPFRAME FPFRAME WE1# WE1# FPLINE FPLINE RD0# DRDY RD1# RD/WR#...
  • Page 23: Block Description

    Epson Research and Development Page 17 Vancouver Design Center 4 Block Description 4.1 Functional Block Diagram 16-bit FPM/EDO DRAM Memory Power Save Register Controller Clocks Display Host FIFO Data CPU / MPU Look-Up Table Control CRTC Bus Clock Memory Clock...
  • Page 24: Look-Up Table

    Page 18 Epson Research and Development Vancouver Design Center 4.2.4 Look-Up Table The Look-Up Table block contains three 16x4 Look-Up Tables, one for each primary color. In monochrome mode only one of these Look-Up Tables is selected and used. 4.2.5 LCD Interface The LCD Interface block performs frame rate modulation for passive LCD panels.
  • Page 25: Pin Out

    Epson Research and Development Page 19 Vancouver Design Center 5 Pin Out 5.1 Pinout Diagram for S1D13504F00A 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...
  • Page 26: Pinout Diagram For S1D13504F01A

    Page 20 Epson Research and Development Vancouver Design Center 5.2 Pinout Diagram for S1D13504F01A 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...
  • Page 27: Pinout Diagram For S1D13504F02A

    Epson Research and Development Page 21 Vancouver Design Center 5.3 Pinout Diagram for S1D13504F02A 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73...
  • Page 28: Pin Description

    Page 22 Epson Research and Development Vancouver Design Center 5.4 Pin Description Key: Input Output Bi-Directional (Input/Output) Power pin CMOS level input CMOS level input with pull-down resistor (typical values of 100K /180K at 5V/3.3V respectively) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
  • Page 29 See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32. This input pin is used to select between the memory and register address spaces of the S1D13504. M/R# is set high to access the memory and low to access the registers. See Section 8.1,...
  • Page 30 Page 24 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin # Reset = Pin Name Type Driver Description F00A 0 Value F02A F01A This pin has multiple functions. • For SH-3 mode, this pin inputs the write enable signal for the lower data byte (WE0#).
  • Page 31: Memory Interface

    Epson Research and Development Page 25 Vancouver Design Center 5.4.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions. • For dual CAS# DRAM, this is the column address strobe for the lower byte (LCAS#).
  • Page 32 Page 26 Epson Research and Development Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A 43, 41, 46, 44, 39, 37, 42, 40, MA[8:0] 35, 34,...
  • Page 33: Lcd Interface

    Epson Research and Development Page 27 Vancouver Design Center 5.4.3 LCD Interface Interface Pin Descriptions Table 5-3: LCD Pin # Reset = Pin Name Type Driver Description F00A 0 Value F02A FPDAT[8:0] 88, 82-75 98, 92-85 CN3 Output 0 Panel Data These pins have multiple functions.
  • Page 34: Crt And External Ramdac Interface

    Page 28 Epson Research and Development Vancouver Design Center 5.4.5 CRT and External RAMDAC Interface Interface Pin Descriptions Table 5-5: CRT and RAMDAC Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions.
  • Page 35 Epson Research and Development Page 29 Vancouver Design Center Interface Pin Descriptions (Continued) Table 5-5: CRT and RAMDAC Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions. • Horizontal Retrace signal for CRT.
  • Page 36: Miscellaneous

    This pin has multiple functions. • When MD9 = 0 at rising edge of RESET#, this pin is an active-low input used to place the S1D13504 into suspend mode; see Section 13, “Power Save Modes” on page 128 for details.
  • Page 37: Summary Of Configuration Options

    Epson Research and Development Page 31 Vancouver Design Center 5.5 Summary of Configuration Options Table 5-8: Summary of Power On / Reset Options value on this pin at rising edge of RESET# is used to configure: (1/0) Pin Name 8-bit host bus interface...
  • Page 38: Multiple Function Pin Mapping

    Page 32 Epson Research and Development Vancouver Design Center 5.6 Multiple Function Pin Mapping Table 5-9: Host Bus Interface Pin Mapping S1D13504 SH-3 MC68K Bus 1 MC68K Bus 2 Generic MPU Pin Names AB[20:1] A[20:1] A[20:1] A[20:1] A[20:1] LDS# DB[15:0]...
  • Page 39: Table 5-11: Lcd, Crt, Ramdac Interface Pin Mapping

    Epson Research and Development Page 33 Vancouver Design Center Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping Monochrome Passive Color Passive Panel Panel Color TFT Panel S1D13504 Single Single Pin Names Single Dual Single Dual Format 1 Format 2 4-bit...
  • Page 40: C. Characteristics

    Page 34 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core V Supply Voltage - 0.3 to 4.6 IO V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to IO V + 0.5...
  • Page 41: Table 6-4: Output Specifications

    Epson Research and Development Page 35 Vancouver Design Center Table 6-4: Output Specifications Symbol Parameter Condition Units Low Level Output Voltage Type 1 - TS1, CO1, TS1D = 3mA Type 2 - TS2, CO2 = 6mA Type 3 - TS3, CO3...
  • Page 42: C. Characteristics

    CSn# WEn# WAIT# D[15:0](write) D[15:0](read) Figure 7-1: SH-3 Interface Timing Note The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value. S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 43: Table 7-1: Sh-3 Interface Timing

    Rising edge RD# to D[15:0] tri-state (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the fall- ing edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later.
  • Page 44: Mc68K Bus 1 Interface Timing (E.g. Mc68000)

    Page 38 Epson Research and Development Vancouver Design Center 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) A[20:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) Figure 7-2: MC68K Bus 1 Interface Timing S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 45: Table 7-2: Mc68K Bus 1 Interface Timing

    AS# or the first positive edge of CLK after A[20:1] and M/R# become val- whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become val- id, whichever occurs later.
  • Page 46: Mc68K Bus 2 Interface Timing (E.g. Mc68030)

    Page 40 Epson Research and Development Vancouver Design Center 7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030) A[20:0] SIZ[1:0] M/R# R/W# DSACK1# D[31:16](write) D[31:16](read) Figure 7-3: MC68K Bus 2 Interface Timing S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 47: Table 7-3: Mc68K Bus 2 Interface Timing

    AS# or the first positive edge of CLK after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later.
  • Page 48: Generic Mpu Interface Synchronous Timing

    Page 42 Epson Research and Development Vancouver Design Center 7.1.4 Generic MPU Interface Synchronous Timing BCLK BCLK A[20:0] Valid M/R# RD0#,RD1# WE0#,WE1# Hi-Z Hi-Z WAIT# Hi-Z Hi-Z Valid D[15:0](write) Hi-Z Hi-Z Valid D[15:0](read) Figure 7-4: Generic MPU Interface Synchronous Timing...
  • Page 49: Table 7-4: Generic Mpu Interface Synchronous Timing

    RD0#, RD1# high to D[15:0] high impedance (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
  • Page 50: Generic Mpu Interface Asynchronous Timing

    Page 44 Epson Research and Development Vancouver Design Center 7.1.5 Generic MPU Interface Asynchronous Timing BCLK BCLK A[20:0] Valid M/R# RD0#,RD1# WE0#,WE1# Hi-Z Hi-Z WAIT# Hi-Z Hi-Z Valid D[15:0](write) Hi-Z Hi-Z D[15:0](read) Valid Figure 7-5: Generic MPU Interface Asynchronous Timing...
  • Page 51: Table 7-5: Generic Mpu Interface Asynchronous Timing

    RD0#, RD1# high to D[15:0] high impedance (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
  • Page 52: Clock Input Requirements

    Page 46 Epson Research and Development Vancouver Design Center 7.2 Clock Input Requirements Clock Input Waveform V IL CLKI Figure 7-6: Clock Input Requirements Table 7-6: Clock Input Requirements Symbol Parameter Units Input Clock Period (CLKI) 12.5 CLKI Pixel Clock Period (PCLK) not shown...
  • Page 53: Memory Interface Timing

    Epson Research and Development Page 47 Vancouver Design Center 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing Memory Clock RAS# CAS# MD(Read) Figure 7-7: EDO-DRAM Read Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 54: Table 7-7: Edo Dram Read Timing

    Page 48 Epson Research and Development Vancouver Design Center Table 7-7: EDO DRAM Read Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 55: Edo-Dram Write Timing

    Epson Research and Development Page 49 Vancouver Design Center 7.3.2 EDO-DRAM Write Timing Memory Clock RAS# CAS# MD(Write) Figure 7-8: EDO-DRAM Write Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 56: Table 7-8: Edo Dram Write Timing

    Page 50 Epson Research and Development Vancouver Design Center Table 7-8: EDO DRAM Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 57: Edo-Dram Read-Write Timing

    Epson Research and Development Page 51 Vancouver Design Center 7.3.3 EDO-DRAM Read-Write Timing Memory Clock RAS# CAS# MD(Read) MD(Write) Figure 7-9: EDO-DRAM Read-Write Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 58: Table 7-9: Edo Dram Read-Write Timing

    Page 52 Epson Research and Development Vancouver Design Center Table 7-9: EDO DRAM Read-Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 59: Edo-Dram Cas Before Ras Refresh Timing

    Epson Research and Development Page 53 Vancouver Design Center 7.3.4 EDO-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1...
  • Page 60: Edo-Dram Self-Refresh Timing

    Page 54 Epson Research and Development Vancouver Design Center 7.3.5 EDO-DRAM Self-Refresh Timing Restarted for Stopped for suspend mode active mode Memory Clock RAS# CAS# Figure 7-11: EDO-DRAM Self-Refresh Timing Table 7-11: EDO-DRAM Self-Refresh Timing Symbol Parameter Units Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1...
  • Page 61: Fpm-Dram Read Timing

    Epson Research and Development Page 55 Vancouver Design Center 7.3.6 FPM-DRAM Read Timing Memory Clock RAS# CAS# MD(Read) Figure 7-12: FPM-DRAM Read Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 62: Table 7-12: Fpm Dram Read Timing

    Page 56 Epson Research and Development Vancouver Design Center Table 7-12: FPM DRAM Read Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 63: Fpm-Dram Write Timing

    Epson Research and Development Page 57 Vancouver Design Center 7.3.7 FPM-DRAM Write Timing Memory Clock RAS# CAS# MD(Write) Figure 7-13: FPM-DRAM Write Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 64: Table 7-13: Fpm-Dram Write Timing

    Page 58 Epson Research and Development Vancouver Design Center Table 7-13: FPM-DRAM Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 65: Fpm-Dram Read-Write Timing

    Epson Research and Development Page 59 Vancouver Design Center 7.3.8 FPM-DRAM Read-Write Timing Memory Clock RAS# CAS# MD(Read) MD(Write) Figure 7-14: FPM-DRAM Read-Write Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 66: Table 7-14: Fpm-Dram Read-Write Timing

    Page 60 Epson Research and Development Vancouver Design Center Table 7-14: FPM-DRAM Read-Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)
  • Page 67: Fpm-Dram Cas# Before Ras# Refresh Timing

    Epson Research and Development Page 61 Vancouver Design Center 7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing Memory Clock RAS# CAS# Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Symbol Parameter Units Memory clock...
  • Page 68: Fpm-Dram Self-Refresh Timing

    Page 62 Epson Research and Development Vancouver Design Center 7.3.10 FPM-DRAM Self-Refresh Timing Restarted for Stopped for suspend mode active mode Memory Clock RAS# CAS# Figure 7-16: FPM-DRAM CBR Self-Refresh Timing Table 7-16: FPM-DRAM CBR Self-Refresh Timing Symbol Parameter Units...
  • Page 69: Display Interface

    Epson Research and Development Page 63 Vancouver Design Center 7.4 Display Interface 7.4.1 Power-On/Reset Timing RESET# RESET# LCD ENABLE (REG[0Dh] bit 0) Inactive Active LCDPWR Active FPFRAME FPLINE Active FPSHIFT FPDAT[15:0] DRDY Figure 7-17: LCD Panel Power-On/Reset Timing Table 7-17: LCD Panel Power-On/Reset Timing...
  • Page 70: Suspend Timing

    Page 64 Epson Research and Development Vancouver Design Center 7.4.2 Suspend Timing SUSPEND# Software Suspend Note 1 Note 2 CLKI LCDPWR Inactive Active Active FPFRAME FPLINE Active Active Inactive DRDY FPSHIFT Active Active FPDAT[15:0] Memory Access Allowed Allowed Not Allowed...
  • Page 71: Single Monochrome 4-Bit Panel Timing

    Epson Research and Development Page 65 Vancouver Design Center 7.4.3 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 UD[3:0], UD[3:0] FPLINE HNDP FPSHIFT 1-317 1-318 1-319 1-320 * Diagram drawn with 2 FPLINE vertical blank period...
  • Page 72: Table 7-19: Single Monochrome 4-Bit Panel A.c. Timing

    Page 66 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing Symbol Parameter Units note 2 FPFRAME setup to FPLINE falling edge...
  • Page 73: Single Monochrome 8-Bit Panel Timing

    Epson Research and Development Page 67 Vancouver Design Center 7.4.4 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-633 1-10 1-634 1-11 1-635 1-12 1-636 1-13 1-637...
  • Page 74: Table 7-20: Single Monochrome 8-Bit Panel A.c. Timing

    Page 68 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units note 2...
  • Page 75: Single Color 4-Bit Panel Timing

    Epson Research and Development Page 69 Vancouver Design Center 7.4.5 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-R1 1-G2 1-B3 1-B319 1-G1 1-B2 1-R4 1-R320 1-G320 1-B1...
  • Page 76: Table 7-21: Single Color 4-Bit Panel A.c. Timing

    Page 70 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] Figure 7-24: Single Color 4-Bit Panel A.C. Timing Table 7-21: Single Color 4-Bit Panel A.C. Timing Symbol Parameter Units note 2 FPFRAME setup to FPLINE falling edge...
  • Page 77: Single Color 8-Bit Panel Timing (Format 1)

    Epson Research and Development Page 71 Vancouver Design Center 7.4.6 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT FPSHIFT2 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12...
  • Page 78: Table 7-22: Single Color 8-Bit Panel A.c. Timing (Format 1)

    Page 72 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 UD[3:0] LD[3:0] Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
  • Page 79: Single Color 8-Bit Panel Timing (Format 2)

    Epson Research and Development Page 73 Vancouver Design Center 7.4.7 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-R1 1-B3 1-G6 1-G638 1-B638 1-G 1...
  • Page 80: Table 7-23: Single Color 8-Bit Panel A.c. Timing (Format 2)

    Page 74 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol...
  • Page 81: Single Color 16-Bit Panel Timing

    Epson Research and Development Page 75 Vancouver Design Center 7.4.8 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE UD[7:0], LD[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-G6 1-B11 1-G635 1-R1 1-G636 1-G12 1-B1 1-R7 1-B7...
  • Page 82: Table 7-24: Single Color 16-Bit Panel A.c. Timing

    Page 76 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[7:0] LD[7:0] Figure 7-30: Single Color 16-Bit Panel A.C. Timing Table 7-24: Single Color 16-Bit Panel A.C. Timing Symbol Parameter Units note 2...
  • Page 83: Dual Monochrome 8-Bit Panel Timing

    Epson Research and Development Page 77 Vancouver Design Center 7.4.9 Dual Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE HNDP FPSHIFT 1-637...
  • Page 84: Table 7-25: Dual Monochrome 8-Bit Panel A.c. Timing

    Page 78 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units note 2...
  • Page 85: Dual Color 8-Bit Panel Timing

    Epson Research and Development Page 79 Vancouver Design Center 7.4.10 Dual Color 8-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241 FPLINE HNDP FPSHIFT 1-G 2 1-G6 1-B7 1-B639 1-R 1...
  • Page 86: Table 7-26: Dual Color 8-Bit Panel A.c. Timing

    Page 80 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-34: Dual Color 8-Bit Panel A.C. Timing Table 7-26: Dual Color 8-Bit Panel A.C. Timing Symbol Parameter Units note 2...
  • Page 87: Dual Color 16-Bit Panel Timing

    Epson Research and Development Page 81 Vancouver Design Center 7.4.11 Dual Color 16-Bit Panel Timing VNDP FPFRAME FPLINE UD[7:0], LD[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE HNDP FPSHIFT UD7, LD7...
  • Page 88: Table 7-27: Dual Color 16-Bit Panel A.c. Timing

    Page 82 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[7:0] LD[7:0] Figure 7-36: Dual Color 16-Bit Panel A.C. Timing Table 7-27: Dual Color 16-Bit Panel A.C. Timing Symbol Parameter Units note 2...
  • Page 89: 16-Bit Tft Panel Timing

    Epson Research and Development Page 83 Vancouver Design Center 7.4.12 16-Bit TFT Panel Timing VNDP FPFRAME FPLINE LINE480 LINE1 LINE480 R[5:1], G[5:0], B[5:1] DRDY FPLINE HNDP HNDP FPSHIFT DRDY R[5:1] 1-640 G[5:0] 1-640 B[5:1] 1-640 Note: DRDY is used to indicate the first pixel...
  • Page 90: Figure 7-38: Tft A.c. Timing

    Page 84 Epson Research and Development Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Figure 7-38: TFT A.C. Timing S1D13504 Hardware Functional Specification X19A-A-002-18 Issue Date: 01/01/30...
  • Page 91: Table 7-28: Tft A.c. Timing

    Epson Research and Development Page 85 Vancouver Design Center Table 7-28: TFT A.C. Timing Symbol Parameter Units Ts (note 1) FPSHIFT period 0.45 FPSHIFT pulse width high 0.45 FPSHIFT pulse width low 0.45 data setup to FPSHIFT falling edge 0.45...
  • Page 92: Crt Timing

    Page 86 Epson Research and Development Vancouver Design Center 7.4.13 CRT Timing Example Timing for 640x480 CRT VNDP VRTC HRTC LINE480 LINE480 DACP[7:0] LINE1 BLANK# HRTC HNDP HNDP DACCLK BLANK# DACD[7:0] 1-640 Figure 7-39: CRT Timing = Vertical Display Period...
  • Page 93: Figure 7-40: Crt A.c. Timing

    Epson Research and Development Page 87 Vancouver Design Center VRTC HRTC HRTC BLANK# DACCLK DACD[7:0] Figure 7-40: CRT A.C. Timing Hardware Functional Specification S1D13504 Issue Date: 01/01/30 X19A-A-002-18...
  • Page 94: Table 7-29: Crt A.c. Timing

    Page 88 Epson Research and Development Vancouver Design Center Table 7-29: CRT A.C. Timing Symbol Parameter Units Ts (note 1) DACCLK period 0.45 DACCLK pulse width high 0.45 DACCLK pulse width low 0.45 data setup to DACCLK rising edge 0.45...
  • Page 95: External Ramdac Read / Write Timing

    Epson Research and Development Page 89 Vancouver Design Center 7.4.14 External RAMDAC Read / Write Timing Read AB[20:0] M/R# DACRS[1:0] Valid RD# Command (depends on CPU bus) DACRD# Write Valid WR# command (depends on CPU bus) DACWR# Figure 7-41: Generic Bus RAMDAC Read / Write Timing...
  • Page 96: Registers

    8 Registers 8.1 Register Mapping The S1D13504 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.
  • Page 97: Memory Configuration Registers

    This bit should be changed only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
  • Page 98: Panel/Monitor Configuration Registers

    Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle. The Half Frame Buffer is idle during vertical non-display periods or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
  • Page 99 Epson Research and Development Page 93 Vancouver Design Center Horizontal Display Width Register REG[04h] Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4...
  • Page 100: Table 8-4: Fpline Polarity Selection

    Page 94 Epson Research and Development Vancouver Design Center HRTC/FPLINE Pulse Width Register REG[07h] HRTC FPLINE HRTC/ HRTC/ HRTC/ HRTC/ Polarity Polarity FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Select Select Width Bit 3 Width Bit 2 Width Bit 1...
  • Page 101 Epson Research and Development Page 95 Vancouver Design Center Vertical Non-Display Period Register REG[0Ah] Vertical Vertical Vertical Vertical Vertical Vertical Vertical Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Period Status Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2...
  • Page 102: Table 8-5: Fpframe Polarity Selection

    Page 96 Epson Research and Development Vancouver Design Center VRTC/FPFRAME Pulse Width Register REG[0Ch] VRTC/ VRTC/ VRTC/ FPFRAME VRTC Polarity FPFRAME FPFRAME FPFRAME Polarity Select Pulse Width Pulse Width Pulse Width Select Bit 2 Bit 1 Bit 0 bit 7 VRTC Polarity Select For CRTs, this bit selects the polarity of the VRTC.
  • Page 103: Display Configuration Registers

    Epson Research and Development Page 97 Vancouver Design Center 8.2.4 Display Configuration Registers Display Mode Register REG[0Dh] Simultaneous Simultaneous Number Of Number Of Number Of Display Display Bits/Pixel Bits/Pixel Bits/Pixel CRT Enable LCD Enable Option Select Option Select Select Bit 2...
  • Page 104: Table 8-7: Number Of Bits-Per-Pixel Selection

    Page 98 Epson Research and Development Vancouver Design Center bits 4-2 Number of Bits-Per-Pixel Select Bits [2:0] These bits select the number of bits-per-pixel (bpp) for the displayed data. Note 15 and 16-bpp modes bypass the LUT and are supported as 12-bpp on passive panels and 15/16- bpp on TFT panels.
  • Page 105 Address registers. The starting address for screen 2 is given by the Screen 2 Display Start Address registers. See Section 10.2, “Image Manipulation” on page 118 and S1D13504 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for more details.
  • Page 106 Page 100 Epson Research and Development Vancouver Design Center Screen 2 Display Start Address Register 0 RW REG[13h] Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5...
  • Page 107: Clock Configuration Register

    15/16 Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register. See Section 10, “Display Configuration” on page 116 and S1D13504 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
  • Page 108: Power Save Configuration Registers

    Page 102 Epson Research and Development Vancouver Design Center 8.2.6 Power Save Configuration Registers Power Save Configuration Register REG[1Ah] Suspend Suspend Software LCD Power Refresh Refresh Suspend Disable Select Bit 1 Select Bit 0 Mode Enable bit 3 LCD Power Disable When this bit = 1 the LCDPWR output is directly forced to the Off state.
  • Page 109 The Half Frame Buffer should be disabled only when idle. The Half Frame Buffer is idle during vertical non-display periods (i.e. when REG[0Ah] bit 7 = 1), or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
  • Page 110 Page 104 Epson Research and Development Vancouver Design Center bit 5 GPIO5 Pin IO Configuration When this bit = 1, GPIO5 is configured as an output. When this bit = 0 (default), GPIO5 is config- ured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and this bit will have no effect on hardware.
  • Page 111 Epson Research and Development Page 105 Vancouver Design Center GPIO Configuration Register 1 REG[1Fh] GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config. IO Config. IO Config. IO Config. bit 3 GPIO11 Pin IO Configuration When this bit = 1, GPIO11 is configured as an output. When this bit = 0 (default), GPIO11 is con- figured as an input.
  • Page 112 Page 106 Epson Research and Development Vancouver Design Center GPIO Status / Control Register 0 REG[20h] GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Pin IO Status IO Status IO Status IO Status...
  • Page 113 LCD backlight power: • When MD9 = 0 at rising edge of RESET#, SUSPEND# is an active-low Schmitt input used to put the S1D13504 into suspend mode - see Section 13, “Power Save Modes” on page 128 for details.
  • Page 114: Table 8-11: Minimum Memory Timing Selection

    DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
  • Page 115: Table 8-12: Ras-To-Cas Delay Timing Select

    Epson Research and Development Page 109 Vancouver Design Center Note that for EDO-DRAM and N = 1.5, this bit is automatically forced to 0 to select 2 MCLK for . This is done to satisfy the CAS# address setup time, t...
  • Page 116: Look-Up Table Registers

    When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen is blanked). This allows the S1D13504 to be dedicated to service CPU to memory accesses. When this bit = 0 the display FIFO is enabled.
  • Page 117 Epson Research and Development Page 111 Vancouver Design Center bits 3-0 LUT Address Bits [3:0] These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU read/write access. The Look-Up Table configuration (e.g. 1/2/4 banks) does not affect the read/write access from the CPU as all 16 positions can be accessed sequentially.
  • Page 118: External Ramdac Control Registers

    Page 112 Epson Research and Development Vancouver Design Center 8.2.9 External RAMDAC Control Registers Note 1. In a Little-Endian architecture, the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register (28h, 2Ah, 2Ch, and 2Eh).
  • Page 119 Epson Research and Development Page 113 Vancouver Design Center RAMDAC Palette Data Register REG[2Eh] or REG[2Fh] RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2...
  • Page 120: Display Buffer

    The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table. Table 9-1: S1D13504 Addressing M/R# Access Register access: •...
  • Page 121: Image Buffer

    Epson Research and Development Page 115 Vancouver Design Center 9.1 Image Buffer The image buffer contains the formatted display data - see Section 10.1, “Display Mode Data Format” on page 116. The displayed image(s) may take up only a portion of the image buffer; the remaining area can be used for multiple images - possibly for animation or general storage.
  • Page 122: Display Configuration

    Page 116 Epson Research and Development Vancouver Design Center 10 Display Configuration 10.1 Display Mode Data Format 1-bpp: bit 7 bit 0 Byte 0 = (A Panel Display Host Address Display Buffer 2-bpp: bit 7 bit 0 Byte 0 Byte 1...
  • Page 123: Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization

    Epson Research and Development Page 117 Vancouver Design Center 15-bpp: 5-5-5 RGB bit 7 bit 0 Byte 0 = (R Byte 1 Passive = (R Byte 2 Panel Display Byte 3 Display Buffer Host Address 16-bpp: 5-6-5 RGB bit 7...
  • Page 124: Image Manipulation

    Page 118 Epson Research and Development Vancouver Design Center 10.2 Image Manipulation The figure below shows how screen 1 and screen 2 images stored in the image buffer are positioned on the display. The screen 1 and screen 2 images can be parts of a larger virtual image or images.
  • Page 125: Clocking

    Epson Research and Development Page 119 Vancouver Design Center 11 Clocking 11.1 Maximum MCLK: PCLK Ratios Table 11-1: Maximum PCLK Frequency with EDO-DRAM Maximum PCLK Allowed Display type 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp • Single Panel.
  • Page 126: Frame Rate Calculation

    Page 120 Epson Research and Development Vancouver Design Center 11.2 Frame Rate Calculation The frame rate is calculated using the following formula: PCLK FrameRate ---------------------------------------------------------------------------------------- - HNDP VNDP Where: = Vertical Display Period = REG[09h] bits [1:0], REG[08h] bits [7:0] + 1...
  • Page 127 Epson Research and Development Page 121 Vancouver Design Center Table 11-3: Example Frame Rates Maximum Maximum Frame Color Minimum DRAM Type Pixel Rate (Hz) Display Resolution Depth Panel (Speed Grade) Clock (bpp) HNDP(T Panel (MHz) • Single Panel. 1/2/4/8 800x600 •...
  • Page 128: Look-Up Table Architecture

    Page 122 Epson Research and Development Vancouver Design Center 12 Look-Up Table Architecture Table 12-1: Look-Up Table Configurations Display Mode 4-Bit Wide Look-Up Table GREEN BLUE Black & White 1 bank of 2 entries 4-level gray 4 banks of 4 entries...
  • Page 129: Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture

    Epson Research and Development Page 123 Vancouver Design Center 2 Bit-Per-Pixel Mode Green Look-Up Table Bank 0 Bank 1 Selected Bank Entry Bank 4-bit display data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0] REG[27h] bits [1:0] 2-bit pixel data Note: the above depiction is intended to show the display data output path only.
  • Page 130: Color Display Modes

    Page 124 Epson Research and Development Vancouver Design Center 12.2 Color Display Modes 1 Bit-Per-Pixel Color Mode Red Look-Up Table Entry 4-bit Red data output Select Logic 1-bit pixel data Green Look-Up Table Entry 4-bit Green data output Select Logic...
  • Page 131: Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture

    Epson Research and Development Page 125 Vancouver Design Center 2 Bit-Per-Pixel Color Mode Red Look-Up Table Bank 0 Bank 1 Selected Bank Entry Bank 4-bit Red data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0]...
  • Page 132: Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture

    Page 126 Epson Research and Development Vancouver Design Center 4 Bit-Per-Pixel Color Mode Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110 4-bit Red data output 0111 Select 1000 Logic 1001 1010 1011 1100 1101 1110 1111 4-bit pixel data...
  • Page 133: Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture

    Epson Research and Development Page 127 Vancouver Design Center 8 Bit-Per-Pixel Color Mode 256 Color Data Format: Red Look-Up Table Bank 0 R2 R1 R0 G2 G1 G0 B1 B0 Selected Bank Entry Bank 4-bit Red data output Select Bank 1...
  • Page 134: Power Save Modes

    Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13504 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend.
  • Page 135: Power Save Mode Function Summary

    Epson Research and Development Page 129 Vancouver Design Center 13.3 Power Save Mode Function Summary Table 13-1: Power Save Mode Function Summary Power Save Mode (PSM) Function Normal Software Hardware (Active) Suspend Suspend Display Active? Register Access Possible? Yes (1)
  • Page 136: Mechanical Data

    Page 130 Epson Research and Development Vancouver Design Center 14 Mechanical Data 14.1 QFP15-128 (S1D13504F00A) QFP15 - 128 pin Unit: mm 16.0 ± 0.4 14.0 ± 0.1 Index 0.16 ± 0.1 0~10° 0.5 ± 0.2 Figure 14-1: Mechanical Drawing QFP15-128...
  • Page 137: Tqfp15-128 (S1D13504F01A)

    Epson Research and Development Page 131 Vancouver Design Center 14.2 TQFP15-128 (S1D13504F01A) TQFP15 - 128 pin Unit: mm ± 0.4 ± 0.1 INDEX +0.05 0.16 - 0.03 +0.05 0.125 - 0.025 0° 10 ° ±0.2 Figure 14-2: Mechanical Drawing TQFP15-128...
  • Page 138: Qfp20-144 (S1D13504F02A)

    Page 132 Epson Research and Development Vancouver Design Center 14.3 QFP20-144 (S1D13504F02A) QFP20 - 144 pin Unit: mm ±0.4 ±0.1 INDEX +0.1 - 0.05 +0.05 0.125 - 0.025 0 ° 10 ° ± 0.2 Figure 14-3: Mechanical Drawing QFP20-144 S1D13504...
  • Page 139: Programming Notes And Examples

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 140 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...
  • Page 141 Introduction ..........7 Programming the S1D13504 Registers ......8 Registers Requiring Special Consideration .
  • Page 142 Identifying the S1D13504 ........
  • Page 143 Table 2-1: Initializing the S1D13504 Registers ....... . . 10 Table 3-1: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer .
  • Page 144 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...
  • Page 145: Introduction

    Vancouver Design Center 1 Introductio n This guide describes how to program the S1D13504 Color Graphics LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13504.
  • Page 146: Programming The S1D13504 Registers

    This section describes how to program the S1D13504 registers that require special consideration. It also provides the correct sequence for initializing the S1D13504 and disabling the half frame buffer. For further information on the any of the registers described below, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.
  • Page 147: Reg[1B] Bit 0 - Half Frame Buffer Disable

    2.2 Register Initialization 2.2.1 Initialization Sequence To initialize the S1D13504 after POWER-ON or a HARDWARE RESET, do the following: Enable the host interface (REG[1Bh] bit 7=0). Disable the display FIFO (REG[23h] bit 7=1) after stopping FIFO accesses to the DRAM.
  • Page 148: Initialization Example

    Example 1: Initialize the registers for a 16 color 640x480 dual passive LCD using a 16 bit data interface; assume 2M byte of display buffer. Program the S1D13504 registers in the following order with the data supplied. Note that for this example, it is assumed that the arrays “unsigned char RED[16], GREEN[16], BLUE[16]” are defined and initialized for the required colors.
  • Page 149: Re-Programming Registers

    Epson Research and Development Page 11 Vancouver Design Center Table 2-1: Initializing the S1D13504 Registers (Continued) REG[20h] = 0x00 General I/O Control REG[21h] = 0x00 REG[24h] = 0x00 Look-Up Table Address for (index = 0; index < 16; ++index) { Update Look-Up Table based on the REG[26h] = RED[index];...
  • Page 150: Display Buffer

    3.1 Display Buffer Location The S1D13504 requires either a 512K byte or a 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block; the S5U13504B00C evalu- ation board decodes the display buffer at the 12M byte location of system memory.
  • Page 151: Memory Organization For Four Bit-Per-Pixel (16 Colors/Gray Shades)

    Epson Research and Development Page 13 Vancouver Design Center 3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades) Two pixels are grouped into one byte of display buffer as shown below: Table 3-3: Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer...
  • Page 152: Memory Organization For 15 Bit-Per-Pixel (32768 Colors)

    Page 14 Epson Research and Development Vancouver Design Center 3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors) One pixel is stored in two bytes of display buffer as shown below: Table 3-5: Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer...
  • Page 153: Look-Up Table (Lut)

    Select Bit 1 Select Bit 0 The S1D13504 LUT Registers are located at offsets 24h, 26h and 27h. They consist of a LUT address register, data register and bank register. Refer to the S1D13504 Hardware Functional Speci- fication document number X19A-A-002-xx for more details.
  • Page 154 Page 16 Epson Research and Development Vancouver Design Center Bank Select Bits LUT banks are provided to give the application developer a choice of colors/gray shades. While the chosen color depth (bpp) may limit the simultaneous colors available, the panel is capable of storing different combinations of colors in banks.
  • Page 155: Look-Up Table Organization

    0 and 0Fh. • The S1D13504 LUT is linear; increasing the LUT number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red Look-Up entry will always result in a bright red output.
  • Page 156 Vancouver Design Center Color Modes In color mode, the S1D13504 supports three, 16 position, 4 bit wide color LUTs (red, green, and blue). Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks. 1 bpp Color In 1 bpp color mode, the LUT is limited to a single 2 entry bank per color.
  • Page 157 Epson Research and Development Page 19 Vancouver Design Center 4 bpp Color In 4 bpp color mode, the LUT is limited to a single 16 entry bank per color. The LUT bank select bits have no effect in this mode.
  • Page 158 =4096 colors. Gray Shade Modes In gray shade mode, the S1D13504 treats the Green LUT as a 16 position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from 1 to 4 banks. 1 bpp Gray Shade The S1D13504 has no true Black-and-White mode.
  • Page 159 8 bpp Gray Shade When the S1D13504 is configured for 8 bpp gray shade mode, bits [7:5] are ignored, bits [4:2] represent the green LUT index, and bits [1:0] are ignored. Only 3 bits of the 8 that actually represent any shade value, therefore the maximum gray shade combination is 8 shades.
  • Page 160 Page 22 Epson Research and Development Vancouver Design Center 15 bpp Gray Shade Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data.
  • Page 161: Advanced Techniques

    The size of the virtual display is limited by the amount of available display buffer. In the case of an S1D13504 with 2M byte of display buffer, the maximum virtual width ranges from 16,368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode. The maximum vertical size at the horizontal maximum is 1025 lines.
  • Page 162: Registers

    “virtual” image. After determining the amount of memory used by each line, do a calculation to see if there is enough memory to support the desired number of lines. Initialize the S1D13504 registers for a 320x240 panel. (See Section 2.2, “Register Initialization” on page 9).
  • Page 163: Panning And Scrolling

    Update the pixel paning register. Note The S1D13504 provides a false indication of vertical non-display period when used with a dual panel display. In this case it is impossible to identify the false signal from the true non-display period. The result is that panning operations at less than 15 bpp may exhibit an occasional tear as the result of updating registers in the wrong order.
  • Page 164: Registers

    Page 26 Epson Research and Development Vancouver Design Center 4.2.1 Registers REG[10h] Screen 1 Display Start Address 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5...
  • Page 165: Examples

    Epson Research and Development Page 27 Vancouver Design Center 4.2.2 Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport. Refer to Section 2.2, “Register Initialization” on page 9 and Section 4.1, “Virtual Display”...
  • Page 166: Split Screen

    The Split Screen feature of the S1D13504 allows a programmer to set up a display for such an appli- cation. The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239.
  • Page 167: Examples

    Epson Research and Development Page 29 Vancouver Design Center REG[13h] Screen 2 Display Start Address Register 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4...
  • Page 168: Lcd Power Sequencing And Power Save Modes

    The S1D13504 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down. Conversely, the LCD signals must be active prior to the power supply starting up.
  • Page 169: Suspend Sequencing

    LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage. Controlling the LCD Drive Power Supply can be done using the S1D13504 LCDPWR# output signal or by 'other' means. The following example assumes that the LCDPWR# pin is being used.
  • Page 170: Suspend Disable Sequence

    Page 32 Epson Research and Development Vancouver Design Center 3. Enable Hardware Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced. 4. Disable Hardware Suspend. 5. Restore the Horzontal and Vertical resolution registers to their original values.
  • Page 171: Crt Considerations

    6 CRT Considerations 6.1 Introduction The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Frame Rate Calculation (Chapter 11)” in S1D13504 Hardware Functional Specification. The following sections describe CRT considerations. 6.1.1 CRT Only For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel.
  • Page 172: Simultaneous Display

    40 MHz and 85 Hz respectively. When pixel depth is less than 8 bpp, the RAMDAC is programmed with the same values as the Look-Up Table. The S1D13504 does not support Simulta- neous Display in a color depth greater than 8 bpp.
  • Page 173 Epson Research and Development Page 35 Vancouver Design Center Table 6-3: 8 bpp Recommended RAMDAC palette data for Simultaneous Display Address Address Address Address Programming Notes and Examples S1D13504 Issue Date: 01/02/01 X19A-G-002-07...
  • Page 174 Page 36 Epson Research and Development Vancouver Design Center Address Address Address Address S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...
  • Page 175 Epson Research and Development Page 37 Vancouver Design Center Table 6-4: Related register data for Simultaneous Display 640X480@75Hz 640X480@60Hz Register Notes PCLK=40.0MHz PCLK=40.0MHz REG[04h] set horizontal display width 0100 1111 0100 1111 REG[05h] set horizontal non-display period 0001 1101 0001 0011...
  • Page 176: Identifying The S1D13504

    Vancouver Design Center 7 Identifying the S1D13504 Unlike previous generations of S1D1350x products, the S1D13504 can be identified at any time after power-on/reset. The S1D13504 and future S1D1350x products can be identified by reading REG[00h]. The value of this register for the S1D13504F00A is 04h.
  • Page 177: Hardware Abstraction Layer (Hal)

    The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and configure the S1D13504. HAL allows easy porting from one S1D1350x product to another and between system architectures. HAL is included in the utilities provided with the S1D13504 evaluation system.
  • Page 178 Page 40 Epson Research and Development Vancouver Design Center int seGetId(int device, BYTE *pId) Description: Reads the revision code register to determine the ID. Parameter: device - registered device ID pId - pointer to allocated byte. The following are the possible values set to *pId:...
  • Page 179: Screen Manipulation

    Epson Research and Development Page 41 Vancouver Design Center int seSetInit(int device) Description: Sets the system to an operational state by initializing memory size, clocks, panel and CRT parameters,... etc. Parameter: device - registered device ID Return Value: ERR_OK - operation completed with no problems...
  • Page 180 Page 42 Epson Research and Development Vancouver Design Center int seGetBitsPerPixel(int device, BYTE *pBitsPerPixel) Description: Determines the color depth of current display mode. Parameter: device - registered device ID pBitsPerPixel - if ERR_OK, *pBitsPerPixel set Return Value: ERR_OK - operation completed with no problems...
  • Page 181 Epson Research and Development Page 43 Vancouver Design Center int seGetScreenSize(int device, int *width, int *height) Description: Determines the width and height of the active display device (LCD or CRT). Parameter: device - registered device ID width - width of display in pixels height - height of display in pixels Return Value: ERR_OK - operation completed with no problems.
  • Page 182 Page 44 Epson Research and Development Vancouver Design Center int seSetBitsPerPixel(int device, BYTE BitsPerPixel) Description: Sets the number of bpp. This function is equivalent to a mode set. Parameter: device - registered device ID BitsPerPixel - desired number of bpp Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
  • Page 183 Epson Research and Development Page 45 Vancouver Design Center int seVirtInit(int device, int xVirt, long *yVirt) Description: Creates a virtual display with the given horizontal size and determines the maximum number of available lines. Parameter: device - registered device ID xVirt - horizontal size of virtual display in pixels.
  • Page 184 Page 46 Epson Research and Development Vancouver Design Center int seWriteDisplayBytes(int device, DWORD addr, BYTE val, DWORD count) Description: Writes one or more bytes to the display buffer. Parameter: device - registered device ID addr - offset from start of the display buffer...
  • Page 185: Color Manipulation

    Epson Research and Development Page 47 Vancouver Design Center 8.2.3 Color Manipulation int seGetDac(int device, BYTE *pDac) Description: Reads the entire DAC into an array. Parameter: device - registered device ID pDac - pointer to an array of BYTE dac[256][3]...
  • Page 186 Page 48 Epson Research and Development Vancouver Design Center int seGetLutEntry(int device, BYTE index, BYTE *pEntry); Description: Reads one LUT entry. Parameter: device - registered device ID index - index to LUT entry (0 to 15) pEntry - pointer to an array of BYTE entry[3]...
  • Page 187 Epson Research and Development Page 49 Vancouver Design Center int seSetLut(int device, BYTE *pLut) Description: Writes the entire LUT from an array into the LUT registers. Parameter: device - registered device ID pLut - pointer to an array of BYTE lut[16][3]...
  • Page 188: Drawing

    Page 50 Epson Research and Development Vancouver Design Center 8.2.4 Drawing int seDrawLine(int device, int x1, int y1, int x2, int y2, DWORD color) Description: Draws a line on the display. Parameter: device - registered device ID. (x1, y1) - top left corner of line...
  • Page 189 Epson Research and Development Page 51 Vancouver Design Center int seFillRect(int device, int x1, int y1, int x2, int y2, DWORD color) Description: Draws a solid rectangle on the display. Parameter: device - registered device ID (x1, y1) - top left corner of rectangle...
  • Page 190: Register Manipulation

    Page 52 Epson Research and Development Vancouver Design Center int seSetPixel(int device, int x, int y, DWORD color) Description: Writes a pixel to the display buffer. Parameter: device - Registered device ID x - horizontal coordinate of the pixel (starting from 0) y - vertical coordinate of the pixel (starting from 0) color - for 1,2,4,8 BPP: refers to index into LUT/DAC.
  • Page 191 Epson Research and Development Page 53 Vancouver Design Center WORD seRotateByteLeft(BYTE val, BYTE bits) Description: Rotates the bits in “val” left as many times as stated in “bits”. Parameter: val - value to rotate bits - how many bits to rotate...
  • Page 192: Sample Code

    Vancouver Design Center 9 Sample Code 9.1 Introduction The following code samples demonstrate two approaches to initializing the S1D13504 color graphics controller with/without using the 13504HAL API. These code samples are for example purposes only. 9.1.1 Sample code using 13504HAL API **------------------------------------------------------------------------- Created 1998, Epson Research &...
  • Page 193: Sample Code Without Using 13504Hal Api

    0, 0xffffffff, 0x200000/4); exit(0); 9.1.2 Sample code without using 13504HAL API **=========================================================================== INIT13504.C - sample code demonstrating the initialization of the S1D13504. Beta release 2.0 98-10-22 The code in this example will perform initialization to the following specification: - 320 x 240 single 8-bit color passive panel.
  • Page 194 0x06, 0x06, 0x0F, 0x09, 0x09, 0x00, 0x0B, 0x0B, 0x00, 0x0D, 0x0D, 0x00, 0x0F, 0x0F, 0x00, ** REGISTER_OFFSET points to the starting address of the S1D13504 registers #define REGISTER_OFFSET ((unsigned char *) 0x1234) void main(void) unsigned char * pRegs; unsigned char * pLUT;...
  • Page 195 Epson Research and Development Page 57 Vancouver Design Center *(pRegs + 0x1B) = 0x00; /* 0000 0000 */ ** Step 2: Disable the display FIFO *(pRegs + 0x23) = 0x80; ** Step 3: Set the memory type ** Register 1: Memory Configuration - 4 ms refresh, EDO *(pRegs + 0x01) = 0x30;...
  • Page 196 Page 58 Epson Research and Development Vancouver Design Center ** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only. *(pRegs + 0x06) = 0x00; /* 0000 0000 */ ** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.
  • Page 197 Epson Research and Development Page 59 Vancouver Design Center ** Register 16-17: Memory Address Offset - this address represents the starting WORD. At 8BPP our 320 pixel width is 160 WORDS *(pRegs + 0x16) = 0xA0; /* 1010 0000 */ *(pRegs + 0x17) = 0x00;...
  • Page 198 Page 60 Epson Research and Development Vancouver Design Center for (idx = 0; idx < 8; idx++) for (rgb = 0; rgb < 3; rgb++) *(pRegs + 0x26) = *pLUT; pLUT++; ** Registers 28-2E: RAMDAC - not used in this example. Programmed very similarly to the LUT but all 256 entries are used.
  • Page 199: Appendix A Supported Panel Values

    Epson Research and Development Page 61 Vancouver Design Center Appendix A Supported Panel Values A.1 Supported Panel Values The following tables show related register data for different panels. All the examples are based on 8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.
  • Page 200 Page 62 Epson Research and Development Vancouver Design Center Table 9-3: TFT Panel TFT 16-Bit Single Register Notes 640X480@47Hz Color REG[02h] set panel type 0010 0101 REG[03h] set MOD rate 0000 0000 REG[04h] set horizontal display width 0100 1111 REG[05h]...
  • Page 201 Suspend Bit 1 Bit 0 2 These bits are used to identify the S1D13504 at power on / RESET. Bit 9 Bit 8 3 When using Little-Endian the RAMDAC should be connected to the low byte of the CPU data bus and the lower...
  • Page 202 S1D13504F00A Register Summary X19A-Q-001-03 6 Simultaneous Display Option Selection Simultaneous Display Option Simultaneous Display Option Select Bits [1:0] Normal Line Doubling Interlace Even Scan Only 7 Number of Bits per Pixel Selection Number Of Bits/Pixel Select Bits [2:0] Number of Bits/Pixel 110-111 Reserved 8 PCLK Divide Selection...
  • Page 203 S1D13504 Color Graphics LCD/CRT Controller 13504CFG.EXE Configuration Program Document Number: X19A-B-001-04...
  • Page 204 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. S1D13504 13504CFG.EXE Configuration Program...
  • Page 205 Epson Research and Development Page 3 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...
  • Page 206 Page 4 Epson Research and Development Vancouver Design Center Table of Contents 13504CFG.EXE ..........7 Program Requirements .
  • Page 207 Epson Research and Development Page 5 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...
  • Page 208 Page 6 Epson Research and Development Vancouver Design Center List of Figures Figure 1: 13504CFG Menu Bar ......... . 10 Figure 2: 13504CFG Open File .
  • Page 209 Epson Research and Development Page 7 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...
  • Page 210: 13504Cfg.exe

    13504CFG gives a software/hardware developer an easy way to modify panel types, modes, etc. for the S1D13504 utilities without recompiling. Once the correct operating environment has been deter- mined, the software/hardware developer can modify the source code manually for a permanent change.
  • Page 211: Program Requirements

    Epson Research and Development Page 9 Vancouver Design Center Program Requirements Video Controller : Any VGA Display Type : LCD or CRT BIOS : Any manufacturer’s VGA BIOS DOS Program : Yes DOS Version : 3.0 or greater Windows Program...
  • Page 212: Script Mode

    Page 10 Epson Research and Development Vancouver Design Center Script Mode In script mode, a file provides 13504CFG with all the information necessary to reconfigure the selected 13504 utility. Any changes which can be made by the interactive user interface can also be done by the script file.
  • Page 213: Interactive Mode

    Epson Research and Development Page 11 Vancouver Design Center Interactive Mode 13504CFG Menu Bar Menu Bar Figure 1: 13504CFG Menu Bar 13504CFG has four main menus: Files, View, Device, and Help. Menu contents can be viewed by using either the mouse or the keyboard.
  • Page 214: Making 13504Cfg Menu Selections

    Page 12 Epson Research and Development Vancouver Design Center Making 13504CFG Menu Selections In 13504CFG, a selection is made by clicking the left mouse button, or by pressing the tab and arrow keys on the keyboard. In the example below, there are three ways to select and open 13504SHOW.EXE in the Files box in the Open File window (figure 2).
  • Page 215: Files Menu

    Epson Research and Development Page 13 Vancouver Design Center Files Menu Figure 3: 13504CFG Files Menu The Files menu contains these functions: • Open - reads the HAL configuration for a given utility. Note A utility must be opened before any other menu command can be executed.
  • Page 216: View Menu

    Notes and Examples” manual, document number X19A-G-002-xx for formulas and other infor- mation. Note Epson R&D Inc. cannot be held liable for damage done to the display as a result of software con- figuration errors. Cancel and Print commands are available in the Current/Advanced Configuration windows. Help is listed, but is not available for this version of 13504CFG.
  • Page 217 Epson Research and Development Page 15 Vancouver Design Center Figure 5: 13504CFG Current Configuration Figure 6: 13504CFG Advanced Configuration (Partial View of Screen) 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...
  • Page 218: Device Menu

    Page 16 Epson Research and Development Vancouver Design Center Device Menu Figure 7: 13504CFG Device Menu The Device menu contains the following sub-menus where parameters for a S1D13504 utility can be edited: • Panel • CRT • Advanced Memory • Power Management •...
  • Page 219: Panel

    Epson Research and Development Page 17 Vancouver Design Center Panel Panel Setup When Panel is selected from the Device menu, the Panel Setup dialog box is displayed. To select a panel assignment, highlight it (in the example window below, “STN 4 Bit Mono Single 320x240”...
  • Page 220 Page 18 Epson Research and Development Vancouver Design Center Edit Panel Setup When a selection is highlighted in the Panel Setup window and Edit is clicked, the Edit Panel Setup window is displayed. The Edit Panel Setup window lists parameters which can be edited, as shown below in Figure 9, “13504CFG Edit Panel Setup.”...
  • Page 221: Crt

    Epson Research and Development Page 19 Vancouver Design Center CRT Setup When CRT is selected from the Device menu, the CRT Setup window is displayed. To select a CRT assignment, highlight it (in the example window below, “CRT 640x400 @ 85Hz, CLKI=33.333MHz”...
  • Page 222 Page 20 Epson Research and Development Vancouver Design Center Edit CRT Setup When a selection is highlighted in the CRT Setup window and Edit is clicked, the Edit CRT Setup window is displayed. The Edit CRT Setup window lists parameters which can be edited, as shown below in Figure 12, “13504CFG Edit CRT Setup.”...
  • Page 223: Advanced Memory

    Epson Research and Development Page 21 Vancouver Design Center Advanced Memory Memory Setup When Advanced Memory is selected from the Device menu, the Memory Setup dialog box is displayed. To select a memory assignment, highlight it ( in the example window below, “Memory Type 0”...
  • Page 224 Page 22 Epson Research and Development Vancouver Design Center Edit Advanced Memory Setup When a selection is highlighted in the Memory Setup window and Edit is clicked, the Edit Advanced Memory Setup window is displayed. The Edit Advanced Memory window lists parameters which can be edited, as shown below in Figure 15, “13504CFG Edit Advanced Memory Setup.”...
  • Page 225: Power Management

    Epson Research and Development Page 23 Vancouver Design Center Power Management Power Setup When Power Management is selected from the Device menu, the Power Setup dialog box is displayed. To select a power assignment, highlight it (in the example window below, “Power Type 0”...
  • Page 226 Page 24 Epson Research and Development Vancouver Design Center Edit Power Setup When a selection is highlighted in the Power Setup window and Edit is clicked, the Edit Power Setup window is displayed. The Edit Power Setup window lists parameters which can be edited, as shown below in Figure 18, “13504CFG Edit Power Setup.”...
  • Page 227: Lookup Table (Lut)

    Epson Research and Development Page 25 Vancouver Design Center Lookup Table (LUT) LUT Setup When Lookup Table is selected from the Device menu, the LUT Setup dialog box is displayed. To select a LUT assignment, highlight it (in the example window below, “LUT Internal 4 Color” is highlighted) and click OK.
  • Page 228 Page 26 Epson Research and Development Vancouver Design Center Edit LUT Setup When a selection is highlighted in the LUT Setup window and Edit is clicked, the Edit LUT Setup window is displayed. The Edit LUT Setup window lists parameters which can be edited, as shown below in Figure 21, “13504CFG Edit LUT Setup.”...
  • Page 229: Setup

    Epson Research and Development Page 27 Vancouver Design Center Setup When Setup is selected from the Device menu, the Setup dialog box is displayed. To select either Register Location, Memory Location, or Memory Size, highlight it (in the example window below, “Register Location: 00C00000 (hex)”...
  • Page 230: Help Menu

    Page 28 Epson Research and Development Vancouver Design Center Setup Parameter Edit When a selection is highlighted in the Setup window and Edit is clicked, a Setup Parameter Edit window is displayed for parameter editing. The Setup Parameter Edit windows for Register Location, Memory Location, and Memory Size respectively are shown below.
  • Page 231: Comments

    Vancouver Design Center Comments It is assumed that the 13504CFG user is familiar with S1D13504 hardware and software. Refer to the S1D13504 “Functional Hardware Specification,” document number X19A-A-002-xx, and the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx for information.
  • Page 232 Page 30 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504CFG.EXE Configuration Program X19A-B-001-04 Issue Date: 01/01/30...
  • Page 233 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 234 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SHOW Demonstration Program X19A-B-002-05 Issue Date: 01/01/30...
  • Page 235 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504SHOW.EXE to a directory that is in the DOS path on your hard...
  • Page 236 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
  • Page 237 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 238 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A-B-003-05 Issue Date: 01/01/30...
  • Page 239 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504SPLT.EXE to a directory that is in the DOS path on your hard...
  • Page 240 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504splt [/a]. Embedded platform: execute 13504splt and at the prompt, type the command line argument. Where: enables manual split screen operation no argument enables automatic split screen operation The following keyboard commands are for navigation within the program.
  • Page 241 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
  • Page 242 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A-B-003-05 Issue Date: 01/01/30...
  • Page 243 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 244 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504VIRT Display Utility X19A-B-004-05 Issue Date: 01/01/30...
  • Page 245 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504VIRT.EXE to a directory that is in the DOS path on your hard...
  • Page 246 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504virt [/A] [/W=???]. Embedded platform: execute 13504virt and at the prompt, type the command line argument. Where: panning and scrolling is performed manually no argument...
  • Page 247 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
  • Page 248 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504VIRT Display Utility X19A-B-004-05 Issue Date: 01/01/30...
  • Page 249 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 250 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PLAY Diagnostic Utility X19A-B-005-05 Issue Date: 01/02/01...
  • Page 251 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504PLAY.EXE to a directory that is in the DOS path on your hard...
  • Page 252 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504play [/?]. Embedded platform: execute 13504play and at the prompt, type the command line argument. Where: /? displays program revision information. The following commands are valid within the 13504PLAY program.
  • Page 253 This causes the file “dumpregs.scr” to be interpreted and the results to be sent to the file “results.” Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the S1D13504 and reads the registers ; Note: after a semi-colon (;), all characters on a line are ignored...
  • Page 254 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
  • Page 255 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 256 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504BMP Demonstration Program X19A-B-006-04 Issue Date: 01/02/01...
  • Page 257 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. 13504BMP Demonstration Program...
  • Page 258 13504CFG configuration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. S1D13504...
  • Page 259 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 260 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A-B-007-04 Issue Date: 01/02/01...
  • Page 261 • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504PWR.EXE to a directory that is in the DOS path on your hard...
  • Page 262 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504pwr [/software /lcd] [/enable /disable] [/i] [/?]. Embedded platform: execute 13504pwr and at the prompt, type the command line argument. Where: selects software suspend...
  • Page 263 13504CFG configuration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. 13504PWR Software Suspend Power Sequencing Utility...
  • Page 264 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A-B-007-04 Issue Date: 01/02/01...
  • Page 265 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation.
  • Page 266 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Configuration Program X19A-B-008-02 Issue Date: 01/02/01...
  • Page 267 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 13504DCFG ..........7 Installation .
  • Page 268 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Configuration Program X19A-B-008-02 Issue Date: 01/02/01...
  • Page 269 Epson Research and Development Page 5 Vancouver Design Center List of Figures Figure 1: General Tab .........
  • Page 270 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Configuration Program X19A-B-008-02 Issue Date: 01/02/01...
  • Page 271: 13504Dcfg

    The header files (chip.h and modex.h) are generated to be used by a software/hardware developer in the development of display drivers. For configuration of the S1D13504 utilities or other programs designed using the S1D13504 HAL, see the 13504CFG Configuration Utility User Manual, document number X19A-B-001-xx.
  • Page 272: 13504Dcfg Configuration Tabs

    3. Save the header file from notepad. Note 13504DCFG is designed to generate header files only. For configuration of the S1D13504 utilities or other programs designed using the S1D13504 HAL, see the 13504CFG Configuration Utility User Manual, document number X19A-B-001-xx. S1D13504...
  • Page 273: General Tab

    Epson Research and Development Page 9 Vancouver Design Center General Tab Figure 1: General Tab The General Tab selects the following general platform settings. General Tab Register Address Starting address of the registers (in hexadecimal). Memory Address Starting address of the display buffer (in hexadecimal).
  • Page 274: Memory Tab

    The values displayed in the “Default” column change Trac based on the Memory Access Time. Suspend Mode Refresh Type of DRAM refresh used while in suspend mode. Installed Memory The amount of memory available to the S1D13504. S1D13504 13504DCFG Configuration Program X19A-B-008-02 Issue Date: 01/02/01...
  • Page 275: Clocks Tab

    Epson Research and Development Page 11 Vancouver Design Center Clocks Tab Figure 3: Clocks Tab The Clocks Tab allows manual selection of either the clocks or the required timings. From this information 13504DCFG calculates the required timings (if clocks are specified) or the required clocks (if timings are specified).
  • Page 276 Selects the frequency of BUSCLK in kHz. Selects the divide ratio used to generate the internal memory MCLK Divide clock (MCLK) from CLKI. Note For further information on clocks, see the S1D13504 Hardware Functional Specifica- tion, document number X19A-A-002-xx. S1D13504 13504DCFG Configuration Program X19A-B-008-02...
  • Page 277: Panel Tab

    Epson Research and Development Page 13 Vancouver Design Center Panel Tab Figure 4: Panel Tab 13504DCFG Configuration Program S1D13504 Issue Date: 01/02/01 X19A-B-008-02...
  • Page 278 Selects between a monochrome and color panel. If no panel Mono/Color exists, select color. Selects format 2 for 8-bit color passive LCD panels. For a description of format 1 and format 2, see the S1D13504 Format 2 Hardware Functional Specification , document number X19A-A-002-xx.
  • Page 279: Crt Tab

    For simultaneous display only. This option is grayed out if simultaneous display is not supported based on the other Simultaneous Display configuration settings. For a summary of Simultaneous Display Options options see the S1D13504 Hardware Functional Specification , document number X19-A-A-002-xx. 13504DCFG Configuration Program S1D13504 Issue Date: 01/02/01...
  • Page 280: Defaults Tab

    Defaults Tab Select the default display device. Three display modes (LCD, Initial Display CRT, and Simultaneous) are saved, but the S1D13504 software initializes the registers based on the default mode. Panel Color Depth Selects the LCD panel initial color depth.
  • Page 281: Registers Tab

    Epson Research and Development Page 17 Vancouver Design Center Registers Tab Figure 7: Registers Tab The Registers Tab lists the register settings that are generated from the chosen configu- ration. Individual register settings may be changed by clicking on the register listing.
  • Page 282: Miscellaneous Flags Tab

    Page 18 Epson Research and Development Vancouver Design Center Miscellaneous Flags Tab Figure 8: Miscellaneous Flags Tab The Miscellaneous Flags Tab changes the cursor flags in the modex.h header file. Modex.h is used by the operating system drivers to determine the type of cursor.
  • Page 283: Saving To A File

    Epson Research and Development Page 19 Vancouver Design Center Saving to a File The register values for a specific configuration can be saved to an ASCII header file for use by a software/hardware developer. 13504DCFG generates the register values in the following format.
  • Page 284: Comments

    Vancouver Design Center Comments • It is assumed that the user is familiar with the S1D13504 controller and software utili- ties. For further information on the S1D13504, refer to the S1D13504 Hardware Func- tional Specification, document number X19A-A-002-xx, and the S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.
  • Page 285 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation.
  • Page 286 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Windows® CE Display Drivers X19A-E-001-04 Issue Date: 01/02/01...
  • Page 287 To build a Windows CE v2.0 display driver for the Hitachi D9000 or ETMA ODO platform follow the instructions below. The instructions assume the S5U13504-D9000 evaluation board is plugged into slots 6 and 7 on the D9000/ODO platform, and the SEIKO EPSON common interface FPGA (ODO.RBF) is used to interface with the S1D13504.
  • Page 288 Modify the file PLATFORM.BIB (using any text editor such as NOTEPAD) to set the default display driver to the file S1D13504.DLL. S1D13504.DLL will be created during the build. Note that PLATFORM.BIB is located in X:\wince\platform\odo\files (where X: is the drive letter).
  • Page 289 10. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\odo\files. The display driver section of PLATFORM.REG should be: ; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values (for the lazy developer types) ;...
  • Page 290 Modify the file CONFIG.BIB (using any text editor such as NOTEPAD) to set the system RAM size and the S1D13504 IO port and display buffer address mapping. Note that CONFIG.BIB is located in X:\wince\platform\cepc\files (where X: is the drive letter). Since...
  • Page 291 11. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\cepc\files. The display driver section of PLATFORM.REG should be: ; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values (for the lazy developer types) ;...
  • Page 292 Follow the procedures from your Hitachi D9000 manual and download the following to the D9000 platform: Download SEIKO EPSON’s common interface FPGA code (ODO.RBF) to the EEPROM of the D9000 system. Download the Windows CE binary ROM image (NK.BIN) to the FLASH memory of the D9000 system.
  • Page 293 • RAMDAC Palette Data Register is REG[2Eh] • The driver is CPU independent but will require another ODO.RBF file to support other CPUs when running on the Hitachi D9000 or ETMA ODO platform. Please check with Seiko Epson for the latest supported CPU ODO files.
  • Page 294 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Windows® CE Display Drivers X19A-E-001-04 Issue Date: 01/02/01...
  • Page 295 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 296 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River WindML v2.0 Display Drivers X19A-E-002-03 Issue Date: 01/04/06...
  • Page 297 The source code is written for portability and contains functionality for most features of the S1D13504. Source code modification is required to provide a smaller, more efficient driver for mass production (e.g. CRT support may be removed for products not requiring a CRT).
  • Page 298 Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2.0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program. These instructions assume that Wind River’s Tornado platform is already installed.
  • Page 299 Mode0.h should be created using the configuration utility 13504DCFG. For more infor- mation on 13504DCFG, see the 13504DCFG Configuration Program User Manual, document number X19A-B-008-xx available at www.erd.epson.com. 7. Open the S1D13504 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13504\8bpp\13504.wsp”...
  • Page 300 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River WindML v2.0 Display Drivers X19A-E-002-03 Issue Date: 01/04/06...
  • Page 301 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
  • Page 302 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River UGL v1.2 Display Drivers X19A-E-003-02 Issue Date: 01/02/01...
  • Page 303 Vancouver Design Center Wind River UGL v1.2 Display Drivers The Wind River UGL v1.2 display drivers for the S1D13504 Color Graphics LCD/CRT Controller are intended as “reference” source code for OEMs developing for Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13504.
  • Page 304 Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1.2 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo software. These instructions assume that the Wind River Tornado platform is correctly installed.
  • Page 305 Mode0.h should be created using the configuration utility 13504DCFG. For more infor- mation on 13504DCFG, see the 13504DCFG Configuration Program User Manual, document number X19A-B-008-xx available at www.erd.epson.com. 6. Open the S1D13504 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13504\8bpp\13504.wsp”...
  • Page 306 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River UGL v1.2 Display Drivers X19A-E-003-02 Issue Date: 01/02/01...
  • Page 307 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 308 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 309 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ......... . . 7 Features .
  • Page 310 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 311 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2-1: Configuration DIP Switch Settings ........8 Table 2-2: Host Bus Selection .
  • Page 312 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 313: Introduction

    This manual describes the setup and operation of the S5U13504B00C Rev. 1.0 Evaluation Board when used with the S1D13504 Color Graphics LCD/CRT Controller in the ISA bus environment. For more information regarding the S1D13504, refer to the S1D13504 Hardware Functional Speci- fication, document number X19A-A-002-xx.
  • Page 314: Installation And Configuration

    Vancouver Design Center 2 Installation and Configuration The S1D13504 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. S1D13504 configuration inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one five-position DIP switch is provided for this purpose. All remaining config- uration inputs are hard-wired.
  • Page 315: Lcd / Ramdac Interface Pin Mapping

    Epson Research and Development Page 9 Vancouver Design Center 3 LCD / RAMDAC Interface Pin Mapping Table 3-1: LCD Signal Connector (J6) Color TFT Color Passive Mono Passive External S1D13504 Connector RAMDAC Pin Names Pin No. 9-bit 12-bit 18-bit 4-bit...
  • Page 316: Cpu / Bus Interface Connector Pinouts

    4 CPU / BUS Interface Connector Pinouts Table 4-1: CPU/BUS Connector (H1) Pinout Connector Comments Pin No. Connected to DB0 of the S1D13504 Connected to DB1 of the S1D13504 Connected to DB2 of the S1D13504 Connected to DB3 of the S1D13504 Ground...
  • Page 317 Table 4-2: CPU/BUS Connector (H2) Pinout Connector Comments Pin No. Connected to AB0 of the S1D13504 Connected to AB1 of the S1D13504 Connected to AB2 of the S1D13504 Connected to AB3 of the S1D13504 Connected to AB4 of the S1D13504...
  • Page 318: Host Bus Interface Pin Mapping

    Page 12 Epson Research and Development Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5-1: Host Bus Interface Pin Mapping S1D13504 SH-3 MC68K Bus 1 MC68K Bus 2 Generic MPU Pin Names AB[20:1] A[20:1] A[20:1] A[20:1] A[20:1] LDS#...
  • Page 319: Technical Description

    D00000h to enable a 16-bit ISA environment. This must be done prior to initializing the S1D13504. Failure to do so will result in the S1D13504 being configured as a 16-bit device (de- fault, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an 8-bit interface.
  • Page 320: Non-Isa Bus Support

    CMOS level output drive of the S1D13504. 6.3 DRAM Support The S1D13504 supports 256K x 16 as well as 1M x 16 DRAM (FPM and EDO) in symmetrical and asymmetrical formats. The S5U13504B00C board supports 5.0V 1M x 16 EDO-DRAM (42-pin SOJ package) in symmet- rical format, providing a 2M byte display buffer.
  • Page 321: Monochrome Lcd Panel Support

    The S1D13504 cannot support 12 or 18-bit TFT panels when CRT is enabled. FPDAT [15:8] is used for RAMDAC data and is not available for LCD. Refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx for details.
  • Page 322: Power Save Modes

    The signal VLCD can be adjusted by R37 to supply an output voltage from -14V to -23V and is enabled/disabled by the S1D13504 control signal LCDPWR. Determine the panel’s specific power requirements and set the potentiometer accordingly before connecting the panel.
  • Page 323: Cpu/Bus Interface Header Strips

    Vancouver Design Center 6.15 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13504 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus. Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout,” on page 10 and Table 4-2 “CPU/BUS Connector (H2) Pinout,”...
  • Page 324: Parts List

    Page 18 Epson Research and Development Vancouver Design Center 7 Parts List Item # Qty/board Designation Part Value Description C13, C14, C19, 10uF 10uF/25V Tantalum D-Size C1-C12, C15-C18 0.01uF 0.01uF, 1206 package C20, C21, C30 0.1uF 0.1uF, 1206 package C23-C25...
  • Page 325 Epson Research and Development Page 19 Vancouver Design Center Item # Qty/board Designation Part Value Description NEC 1Mx16 , EDO, Self-Refresh, DRAM, SOJ UPD4218S165LE-50 package TIBPAL22V10-15BCNT Texas Instrument PAL 24 pin DIP package/socketed Osc. -14 Fox 40.0MHz Oscillator or equiv. 14 pin DIP/socketed...
  • Page 326: Schematic Diagrams

    Page 20 Epson Research and Development Vancouver Design Center 8 Schematic Diagrams Figure 1: S1D13504B00C Schematic Diagram (1 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 327 Epson Research and Development Page 21 Vancouver Design Center Figure 2: S1D13504B00C Schematic Diagram (2 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...
  • Page 328 Page 22 Epson Research and Development Vancouver Design Center Figure 3: S1D13504B00C Schematic Diagram (3 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 329 Epson Research and Development Page 23 Vancouver Design Center Figure 4: S1D13504B00C Schematic Diagram (4 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...
  • Page 330 Page 24 Epson Research and Development Vancouver Design Center Figure 5: S1D13504B00C Schematic Diagram (5 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 331 Epson Research and Development Page 25 Vancouver Design Center DC_OUT DC_OUT VOUT_ADJ DC_OUT VOUT_ADJ REMOTE DC_IN DC_IN DC_IN Figure 6: S1D13504B00C Schematic Diagram (6 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...
  • Page 332 Page 26 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...
  • Page 333 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 334 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 335 Features ..........8 S1D13504 Color Graphics LCD Controller ......8 2.1.1...
  • Page 336 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 337 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2-1: LCD Connector Pinout ........10 Table 3-1: Interface Signals .
  • Page 338 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 339: Introduction

    FPGA / processor combination. This manual describes how the S5U13504-D9000 Evaluation Board is used to provide a color LCD solution for the Windows CE environment. Reference S1D13504 Hardware Functional Specification, document number X19A-A-002-xx. D9000 Development System, Hardware User Manual - Hitachi. Evaluation Board User Manual...
  • Page 340: Features

    CPUs and LCD displays. The S1D13504 supports LCD interfaces with data widths up to 16 bits. Using Frame Rate Modulation (FRM), it can display 16 shades of gray on monochrome panels, up to 4096 colors on passive panels and 64K colors on active matrix TFTs.
  • Page 341: Lcd Display Support

    Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Display Support The S1D13504 provides a wide range of flexibility for display type and resolution. Display types include: • 4/8-bit monochrome passive. • 4/8/16-bit color passive. • Active matrix TFT.
  • Page 342: Lcd Interface Pin Mapping

    Page 10 Epson Research and Development Vancouver Design Center 2.1.3 LCD Interface Pin Mapping Table 2-1: LCD Connector Pinout Pin # Color TFT Color Passive Mono Passive Comments S1D13504 Pin Names 9-bit 12-bit 18-bit 4-bit 8-bit 16-bit 4-bit 8-bit FPSHIFT...
  • Page 343: Crt Support

    Page 11 Vancouver Design Center 2.1.4 CRT Support The S1D13504 has all the necessary signals to interface to an external RAMDAC so a CRT is supported. The Brooktree Bt481A RAMDAC is supported on the S5U13504-D9000 evaluation board. Refer to the Programming Notes and Examples, document number X19A-G-002-xx for programming details.
  • Page 344: D9000 Specifics

    Vancouver Design Center 3 D9000 Specifics 3.1 Interface Signals The S1D13504 is intended for direct connection to most processors, so the FPGA in this environment simply acts as a pass-through for the required processor interface signals. Table 3-1: Interface Signals...
  • Page 345 Epson Research and Development Page 13 Vancouver Design Center Table 3-2: Connector Pinout for Channel A7 (Continued) Channel A7 Pin # FPGA Signal S1D13504 Signal Pin # FPGA Signal S1D13504 Signal chA7p4 chA7p5 dc3v DC3V chA7p6 chA7p7 dc3vs chA7p8 chA7p9...
  • Page 346 Page 14 Epson Research and Development Vancouver Design Center Table 3-2: Connector Pinout for Channel A7 (Continued) Channel A7 Pin # FPGA Signal S1D13504 Signal Pin # FPGA Signal S1D13504 Signal chA7p11 chA7p12 chA7p13 chA7p34 chA7p14 chA7p15 chA7p16 chA7p17 chA7p33...
  • Page 347 Epson Research and Development Page 15 Vancouver Design Center Table 3-3: Connectors Pinout for Channel A6 Channel A6 Pin # FPGA Signal S1D13504 Signal Pin # FPGA Signal S1D13504 Signal SmXY chA6p1 dc5v DC5V chA6p2 chA6p3 WE0# dc3v DC3V chA6p4...
  • Page 348 Page 16 Epson Research and Development Vancouver Design Center Table 3-3: Connectors Pinout for Channel A6 (Continued) Channel A6 Pin # FPGA Signal S1D13504 Signal Pin # FPGA Signal S1D13504 Signal chA6p11 M/R# chA6p12 chA6p13 WE1# chA6p34 chA6p14 RESET# chA6p15...
  • Page 349: Bus Interface Timing

    Where 1 = closed/on and 0 = open/off 3.1.3 Memory Address (CS#, M/R#) Decode The S1D13504 is a memory-mapped device for both the registers and display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are: •...
  • Page 350: Parts List

    Page 18 Epson Research and Development Vancouver Design Center 3.4 Parts List Item # Qty. Reference Part Description C1,C2,C3,C4,C5,C6,C7, C8,C9,C11,C12,C13,C14, C15,C16,C21,C26,C27, 0.1uF 0.1uF, 0805 pckg C28,C29,C34,C35,C36, 10uF 10uF / 20V Tantalum C-Size Electrolytic, Radial Lead 35V +/- 20% Nippon / United...
  • Page 351: Schematic Diagrams

    Epson Research and Development Page 19 Vancouver Design Center 3.5 Schematic Diagrams Figure 3-1: S5U13504-D9000 Schematic Diagram (1 of 4) Evaluation Board User Manual S5U13504-D9000 Issue Date: 01/02/02 X19A-G-003-05...
  • Page 352 Page 20 Epson Research and Development Vancouver Design Center Figure 3-2: S5U13504-D9000 Schematic Diagram (2 of 4) S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 353 Epson Research and Development Page 21 Vancouver Design Center DC_OUT VOUT_ADJ REMOTE DC_IN Figure 3-3: S5U13504-D9000 Schematic Diagram (3 of 4) Evaluation Board User Manual S5U13504-D9000 Issue Date: 01/02/02 X19A-G-003-05...
  • Page 354 Page 22 Epson Research and Development Vancouver Design Center Figure 3-4: S5U13504-D9000 Schematic Diagram (4 of 4) S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 355: Pcb Layout

    Epson Research and Development Page 23 Vancouver Design Center 3.5.1 PCB Layout 3.5.2 Component Placement Figure 3-5: Component Placement Evaluation Board User Manual S5U13504-D9000 Issue Date: 01/02/02 X19A-G-003-05...
  • Page 356: Perspective View

    Page 24 Epson Research and Development Vancouver Design Center 3.5.3 Perspective View S1D13504 RAMDAC LCD Power Supply CRT Connector DRAM LCD Connector Figure 3-6: S5U13504-D9000 Perspective View S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02...
  • Page 357 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 358 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Power Consumption X19A-G-006-04 Issue Date: 01/02/02...
  • Page 359 – the higher the divide, the lower the power consumption. There are two power save modes in the S1D13504: Software and Hardware SUSPEND. The power consumption of these modes is also affected by various system design variables.
  • Page 360 LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13504 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
  • Page 361 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 362 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-08 Issue Date: 01/02/02...
  • Page 363 Interfacing to the PR31500/PR31700 ......8 S1D13504 Host Bus Interface ......9 Generic MPU Host Bus Interface Pin Mapping .
  • Page 364 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-08 Issue Date: 01/02/02...
  • Page 365 Table 5-2: PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E ..19 Table 5-3: S1D13504 Configuration using the IT8368E ..... . . 20 Table 5-4: S1D13504 Host Bus Selection using the IT8368E.
  • Page 366 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-08 Issue Date: 01/02/02...
  • Page 367: Introduction

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Philips MIPS PR31500/PR31700 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
  • Page 368: Interfacing To The Pr31500/Pr31700

    2 Interfacing to the PR31500/PR31700 The Philips PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13504 connects to the PR31500/PR31700 processor. The S1D13504 can be successfully interfaced using one of three configurations: •...
  • Page 369: S1D13504 Host Bus Interface

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
  • Page 370: Generic Mpu Host Bus Interface Signals

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
  • Page 371: Direct Connection To The Philips Pr31500/Pr31700

    Oscillator CLKI Note: When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection Note For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.
  • Page 372: Memory Mapping And Aliasing

    The S1D13504 also has internal clock dividers providing additional flexibility. 4.2 Memory Mapping and Aliasing The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the PR31500/PR31700) to the M/R# input of the S1D13504.
  • Page 373: S1D13504 Configuration

    Vancouver Design Center 4.3 S1D13504 Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.
  • Page 374: System Design Using The It8368E Pc Card Buffer

    S1D13504 can be interfaced with the PR31500/PR31700 without using a PC Card slot. Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot.
  • Page 375 Asynchronous Timing (for details refer to the S1D13504 Hardware Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
  • Page 376 Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether...
  • Page 377: Hardware Description-Using Two It8368E's

    Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
  • Page 378: It8368E Configuration

    When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13504. When accessing the S1D13504 the associated card-side signals are disabled in order to avoid any conflicts.
  • Page 379: Memory Mapping And Aliasing

    When the PR31500/PR31700 accesses the PC Card slots buffered through the ITE IT8368E, bits CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the PR31500/PR31700 is divided into Attribute, IO and S1D13504 access. Table 5-2:, “PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E” provides all the details of the Attribute/IO address re-allocation by the IT8368E.
  • Page 380: S1D13504 Configuration

    Vancouver Design Center 5.5 S1D13504 Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.
  • Page 381: Software

    Vancouver Design Center 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.
  • Page 382: References

    • Epson Research and Development, Inc., S1D13504 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.
  • Page 383: Technical Support

    Epson Research and Development Page 23 Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13504) Taiwan, R.O.C. North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
  • Page 384 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-08 Issue Date: 01/02/02...
  • Page 385 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 386 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-07 Issue Date: 01/02/02...
  • Page 387 LCD Memory Access Cycles ......9 S1D13504 Host Bus Interface ......10 Generic MPU Host Bus Interface Pin Mapping .
  • Page 388 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-07 Issue Date: 01/02/02...
  • Page 389 Table 4-2: Host Bus Interface Selection ....... . 13 Table 4-2: NEC/S1D13504 Truth Table ....... . 14 List of Figures Figure 2-1: NEC VR4102 Read/Write Cycles .
  • Page 390 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-07 Issue Date: 01/02/02...
  • Page 391: Introduction

    Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the NEC 4102 Microprocessor (uPD30102). The NEC V 4102 Microprocessor is specifically...
  • Page 392: Interfacing To The Nec Vr4102

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2.1 The NEC VR4102 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE-based embedded consumer applications in mind, the VR4102 offers a highly integrated solution for portable systems.
  • Page 393: Lcd Memory Access Cycles

    Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle.
  • Page 394: S1D13504 Host Bus Interface

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
  • Page 395: Generic Mpu Host Bus Interface Signals

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
  • Page 396: Vr4102 To S1D13504 Interface

    Notes: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec. When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).