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Epson S1D13506 Technical Manual

Color lcd/crt/tv controller
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S1D13506 Color LCD/CRT/TV Controller
S1D13506
TECHNICAL MANUAL
Document Number: X25B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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  • Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...
  • Page 3: Riesstrasse

    Epson Research and Development Page 3 Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical manuals • Evaluation/Demonstration board manual Evaluation/Demonstration Board •...
  • Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...
  • Page 5 S1D13506 COLOR LCD/CRT/TV CONTROLLER March 2001 The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
  • Page 6 Copyright ©1998, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document.
  • Page 7: Hardware Functional Specification

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 8 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 9: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........17 Scope .
  • Page 10 Registers ........124 Initializing the S1D13506 ......124 8.1.1...
  • Page 11: Issue Date: 02/03/26 Page

    Epson Research and Development Page 5 Vancouver Design Center 8.3.2 General IO Pins Registers ....... 126 8.3.3...
  • Page 12 15.4.3 Limitations ........208 16 EPSON Independent Simultaneous Display (EISD) ....209 16.1 Introduction .
  • Page 13 Epson Research and Development Page 7 Vancouver Design Center 19.1 Display Modes ......221 19.2 Power Save Mode .
  • Page 14 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 15 Epson Research and Development Page 9 Vancouver Design Center List of Tables Table 5-1: Host Bus Interface Pin Descriptions ......29 Table 5-2: Memory Interface Pin Descriptions .
  • Page 16 Page 10 Epson Research and Development Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing..... . . 83 Table 7-23: Single Monochrome 8-Bit Panel A.C.
  • Page 17 Table 10-1: S1D13506 Addressing ........181...
  • Page 18 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 19 Figure 3-10: Typical System Diagram (Toshiba MIPS TX3912 Bus) ....26 Figure 4-1: S1D13506 Block Diagram ....... . . 27 Figure 5-1: Pinout Diagram .
  • Page 20 Page 14 Epson Research and Development Vancouver Design Center Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing ..... . .85 Figure 7-26: Single Color 4-Bit Panel Timing .
  • Page 21 Epson Research and Development Page 15 Vancouver Design Center Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL ..195 Figure 14-1: Ink/Cursor Data Format ....... . . 197 Figure 14-2: Unclipped Cursor Positioning .
  • Page 22 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 23: Introduction

    1.2 Overview Description The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
  • Page 24: Features

    • The complete 2M byte display buffer address space is directly and contiguously avail- able through the 21-bit address bus. 2.2 CPU Interface • Supports the following interfaces: • Epson E0C33 (16-bit interface to 32-bit microprocessor). • Hitachi SH-4 bus interface. • Hitachi SH-3 bus interface. • MIPS/ISA.
  • Page 25: Display Support

    2.5 Display Features • SwivelView™: 90°, 180°, 270° hardware rotation of display image. • EPSON Independent Simultaneous Display (EISD): displays independent images on different displays (CRT or TV and passive or TFT/D-TFD panel). • Virtual Display Support: displays images larger than the panel size through the use of panning and scrolling.
  • Page 26: Clock Source

    Page 20 Epson Research and Development Vancouver Design Center 2.6 Clock Source • Memory clock can be derived from CLKI or BUSCLK pin. It can be internally divided by 2. • Pixel clock can be derived from CLKI, CLKI2, or BUSCLK pin. It can be internally divided by 2, 3 or 4.
  • Page 27: Typical System Implementation Diagrams

    Epson Research and Development Page 21 Vancouver Design Center 3 Typical System Implementation Diagrams For the pin mapping of each system implementation, see Table 5-7:, “CPU Interface Pin Mapping,” on page 40. Oscillator Oscillator Generic 4-bit FPDAT[7:4] L[3:0] Single FPSHIFT...
  • Page 28: Figure 3-2: Typical System Diagram (Hitachi Sh-4 Bus)

    Page 22 Epson Research and Development Vancouver Design Center Oscillator Oscillator SH-4 4-bit FPDAT[7:4] D[3:0] A[21] M/R# Single FPSHIFT FPSHIFT CSn# A[20:1] AB[20:1] Display FPFRAME FPFRAME D[15:0] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# WE1# S1D13506 RD/WR# GPIOx RD/WR# RED,GREEN,BLUE...
  • Page 29: Figure 3-4: Typical System Diagram (Mc68K Bus 1, Motorola 16-Bit 68000)

    Epson Research and Development Page 23 Vancouver Design Center Oscillator Oscillator MC68000 WE0# FPDAT[7:4] UD[3:0] 8-bit FPDAT[3:0] LD[3:0] A[23:21] M/R# Decoder Dual FC0, FC1 FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506...
  • Page 30: Figure 3-6: Typical System Diagram (Motorola Powerpc Bus)

    Page 24 Epson Research and Development Vancouver Design Center Oscillator Oscillator PowerPC A[0:10] M/R# Decoder 16-bit FPDAT[15:0] D[15:0] Single Decoder FPSHIFT FPSHIFT A[11:31] AB[20:0] FPFRAME FPFRAME Display D[0:15] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# S1D13506 RD/WR# GPIOx RD/WR# TSIZ0...
  • Page 31: Figure 3-8: Typical System Diagram (Pc Card Bus)

    Epson Research and Development Page 25 Vancouver Design Center Oscillator Oscillator PC Card FPDAT[15:8] UD[7:0] 16-bit FPDAT[7:0] LD[7:0] Decoder M/R# A[25:21] Dual FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506 WE0# CE2#...
  • Page 32: Figure 3-10: Typical System Diagram (Toshiba Mips Tx3912 Bus)

    Page 26 Epson Research and Development Vancouver Design Center Oscillator Oscillator TX3912 M/R# FPDAT[11:0] D[11:0] 12-bit AB[16:13] FPSHIFT FPSHIFT A[12:0] AB[12:0] D[23:16] DB[15:8] FPFRAME FPFRAME Display D[31:24] DB[7:0] AB20 FPLINE FPLINE CARDREG* AB19 DRDY DRDY (MOD) S1D13506 CARDIORD* AB18 CARDIOWR*...
  • Page 33: Internal Description

    Page 27 Vancouver Design Center 4 Internal Description 4.1 Block Diagram Showing Pipelines DRAM MediaPlug Camera Memory Controller Host Pipeline CRT/TV CRT/TV Pipeline Register Encoder Power Save Figure 4-1: S1D13506 Block Diagram Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 34: Pins

    Page 28 Epson Research and Development Vancouver Design Center 5 Pins 5.1 Pinout Diagram 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...
  • Page 35: Pin Description

    Epson Research and Development Page 29 Vancouver Design Center 5.2 Pin Description Key: Input Output Bi-Directional (Input/Output) Analog Power pin CMOS level input CMOS level input with pull down resistor (typical values of 50Ω/90ΚΩ at 5V/3.3V respectively) CMOS level Schmitt input...
  • Page 36 Page 30 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State • For Philips PR31500/31700 Bus, these pins are connected to V • For Toshiba TX3912 Bus, these pins are connected to V •...
  • Page 37 • For all other busses, this input pin is used to select between the M/R# Hi-Z display buffer and register address spaces of the S1D13506. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping.
  • Page 38 This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13506 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#).
  • Page 39 Epson Research and Development Page 33 Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).
  • Page 40 Page 34 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see “Summary of Configuration Options”.
  • Page 41: Memory Interface

    Epson Research and Development Page 35 Vancouver Design Center 5.2.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State • For dual-CAS# DRAM, this is the column address strobe for the lower byte (LCAS#).
  • Page 42 Page 36 Epson Research and Development Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State 58, 60, 62, Multiplexed memory address - see Memory Interface Timing on page MA[8:0] 64, 66, 67, 70 for detailed functionality.
  • Page 43: Lcd Interface

    Epson Research and Development Page 37 Vancouver Design Center 5.2.3 LCD Interface Table 5-3: LCD Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State Panel data bus. Not all pins are used for some panels - see Table 5-9:, “LCD Interface Pin Mapping,”...
  • Page 44: Crt Interface

    Page 38 Epson Research and Development Vancouver Design Center 5.2.4 CRT Interface Table 5-4: CRT Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State HRTC Horizontal retrace signal for CRT VRTC Vertical retrace signal for CRT no output...
  • Page 45: Summary Of Configuration Options

    Epson Research and Development Page 39 Vancouver Design Center 5.3 Summary of Configuration Options Table 5-6: Summary of Power-On/Reset Options Pin Name value of this pin at rising edge of RESET# is used to configure:(1/0) Not used, value of this pin at rising edge of RESET# can be read at REG[00Ch] bit 0...
  • Page 46: Multiple Function Pin Mapping

    Note AB0 is not used internally for these busses and must be connected to either V For further information on interfacing the S1D13506 to the PC Card bus, see Interfac- ing to the PC Card Bus, document number X25B-G-005-xx. S1D13506...
  • Page 47: Table 5-8: Memory Interface Pin Mapping

    Epson Research and Development Page 41 Vancouver Design Center Table 5-8: Memory Interface Pin Mapping FPM/EDO-DRAM S1D13506 Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 Pin Names 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# MD[15:0] D[15:0] MA[8:0] A[8:0] GPIO3...
  • Page 48: Table 5-9: Lcd Interface Pin Mapping

    Page 42 Epson Research and Development Vancouver Design Center Table 5-9: LCD Interface Pin Mapping Monochrome Passive Color Passive Panel Panel S1D13506 Color TFT/D-TFD Panel Single Single Single Dual Single Single Dual Names Format 1 Format 2 4-bit 8-bit 8-bit...
  • Page 49: Table 5-10: Ma11, Ma10, Ma9, And Drdy Pin Mapping

    Epson Research and Development Page 43 Vancouver Design Center Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping MD14, MD7, MD6 MA11 MA10 DRDY GPIO2 GPIO1 GPIO3 DRDY GPIO2 GPIO1 DRDY GPIO2 GPIO1 DRDY MA11 MA10 DRDY VMPEPWR GPIO1 GPIO3...
  • Page 50: Crt/Tv Interface

    Page 44 Epson Research and Development Vancouver Design Center 5.5 CRT/TV Interface The following figure shows external circuitry for the CRT/TV interface. CRT/TV CRT Only CRT Only (REG[05Bh] bit 3 = 0) (REG[05Bh] bit 3 =1) (REG[05Bh] bit 3 =1) DAC V = 3.3V...
  • Page 51: C. Characteristics

    Epson Research and Development Page 45 Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Supply Voltage - 0.3 to 6.0 DAC V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to V + 0.5...
  • Page 52: Table 6-4: Electrical Characteristics For Vdd = 3.3V Typical

    Page 46 Epson Research and Development Vancouver Design Center Table 6-4: Electrical Characteristics for VDD = 3.3V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -2mA (Type1), High Level Output Voltage - 0.3...
  • Page 53: Table 6-5: Electrical Characteristics For Vdd = 3.0V Typical

    Epson Research and Development Page 47 Vancouver Design Center Table 6-5: Electrical Characteristics for VDD = 3.0V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -1.8mA (Type1), High Level Output Voltage - 0.3...
  • Page 54: C. Characteristics

    Page 48 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: = 3.0V ± 10% and V = 5.0V ± 10% = -40° C to 85° C and T for all inputs must be < 5 ns (10% ~ 90%)
  • Page 55: Table 7-1: Generic Timing

    Epson Research and Development Page 49 Vancouver Design Center Table 7-1: Generic Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,...
  • Page 56: Hitachi Sh-4 Interface Timing

    (BUSCLK input is not divided). Note The SH-4 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. The SH-4 read-to-write idle cycle transition must be set to a non-zero value (with reference to BUSCLK).
  • Page 57: Table 7-2: Hitachi Sh-4 Timing

    Epson Research and Development Page 51 Vancouver Design Center Table 7-2: Hitachi SH-4 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...
  • Page 58: Hitachi Sh-3 Interface Timing

    BUSCLK cannot be divided by 2 in SH-3 interface mode. MD12 must be set to 0 (BUSCLK input is not divided). Note The SH-3 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. S1D13506...
  • Page 59: Table 7-3: Hitachi Sh-3 Timing

    Epson Research and Development Page 53 Vancouver Design Center Table 7-3: Hitachi SH-3 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...
  • Page 60: Mips/Isa Interface Timing (E.g. Nec Vr41Xx)

    Page 54 Epson Research and Development Vancouver Design Center 7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) BUSCLK BUSCLK LatchA20 SA[19:0] M/R#, SBHE# MEMR# MEMW# IOCHRDY SD[15:0](write) SD[15:0](read) Figure 7-4: MIPS/ISA Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 61: Table 7-4: Mips/Isa Timing

    Epson Research and Development Page 55 Vancouver Design Center Table 7-4: MIPS/ISA Timing 3.0V 5.0V Symbol Parameter Units Clock frequency BUSCLK Clock period BUSCLK BUSCLK BUSCLK Clock pulse width high Clock pulse width low LatchA20, SA[19:0], M/R#, SBHE# setup to first...
  • Page 62: Motorola Mc68K Bus 1 Interface Timing (E.g. Mc68000)

    Page 56 Epson Research and Development Vancouver Design Center 7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) A[20:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) Figure 7-5: Motorola MC68000 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 63: Table 7-5: Motorola Mc68000 Timing

    Epson Research and Development Page 57 Vancouver Design Center Table 7-5: Motorola MC68000 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and...
  • Page 64: Motorola Mc68K Bus 2 Interface Timing (E.g. Mc68030)

    Page 58 Epson Research and Development Vancouver Design Center 7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) A[20:0] SIZ[1:0] M/R# R/W# DSACK1# D[31:16](write) D[31:16](read) Figure 7-6: Motorola MC68030 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 65: Table 7-6: Motorola Mc68030 Timing

    Epson Research and Development Page 59 Vancouver Design Center Table 7-6: Motorola MC68030 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0,...
  • Page 66: Motorola Powerpc Interface Timing (E.g. Mpc8Xx, Mc68040, Coldfire)

    Page 60 Epson Research and Development Vancouver Design Center 7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) CLKOUT CLKOUT A[11:31], RD/WR# TSIZ[0:1], M/R# t15 t16 D[0:15](write) D[0:15](read) Figure 7-7: Motorola PowerPC Timing Note BUSCLK cannot be divided by 2 in PowerPC interface mode. MD12 must be set to 0 (BUSCLK input is not divided).
  • Page 67: Table 7-7: Motorola Powerpc Timing

    Epson Research and Development Page 61 Vancouver Design Center Table 7-7: Motorola PowerPC Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CLKOUT Clock period CLKOUT CLKOUT CLKOUT Clock pulse width low Clock pulse width high AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup...
  • Page 68: Pc Card Timing (E.g. Strongarm)

    Page 62 Epson Research and Development Vancouver Design Center 7.1.8 PC Card Timing (e.g. StrongARM) (provided externally) A[20:1] M/R# CE1#, CE2# WAIT# D[15:0](write) D[15:0](read) Figure 7-8: PC Card Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 69: Table 7-8: Pc Card Timing

    Epson Research and Development Page 63 Vancouver Design Center Table 7-8: PC Card Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either...
  • Page 70: Philips Interface Timing (E.g. Pr31500/Pr31700)

    Page 64 Epson Research and Development Vancouver Design Center 7.1.9 Philips Interface Timing (e.g. PR31500/PR31700) DCLKOUT DCLKOUT ADDR[12:0] /CARDREG /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD /CARDxWAIT D[31:16](write) D[31:16](read) Figure 7-9: Philips Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 71: Table 7-9: Philips Timing

    Epson Research and Development Page 65 Vancouver Design Center Table 7-9: Philips Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...
  • Page 72: Toshiba Interface Timing (E.g. Tx39Xx)

    Page 66 Epson Research and Development Vancouver Design Center 7.1.10 Toshiba Interface Timing (e.g. TX39xx) DCLKOUT DCLKOUT ADDR[12:0] CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) Figure 7-10: Toshiba Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 73: Table 7-10: Toshiba Timing

    Epson Research and Development Page 67 Vancouver Design Center Table 7-10: Toshiba Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...
  • Page 74: Clock Timing

    Page 68 Epson Research and Development Vancouver Design Center 7.2 Clock Timing 7.2.1 Input Clocks V IL Figure 7-11: CLKI Clock Input Requirements Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally Symbol Parameter Units Input Clock Frequency Input Clock Period...
  • Page 75: Internal Clocks

    Epson Research and Development Page 69 Vancouver Design Center 7.2.2 Internal Clocks Table 7-13: Internal Clock Requirements Symbol Parameter Units Memory Clock Frequency MCLK LCD Pixel Clock Frequency LCD PCLK CRT/TV Pixel Clock Frequency Note 1 CRT/TV PCLK MediaPlug Clock Frequency MediaPlug Clock 1.
  • Page 76: Memory Interface Timing

    Page 70 Epson Research and Development Vancouver Design Center 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE# (read) MD (read) WE#(write) t20 t21 MD(write) Figure 7-12: EDO-DRAM Page Mode Timing...
  • Page 77: Table 7-14: Edo-Dram Read, Write, Read-Write Timing

    Epson Research and Development Page 71 Vancouver Design Center Table 7-14: EDO-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
  • Page 78: Edo-Dram Cas Before Ras Refresh Timing

    Page 72 Epson Research and Development Vancouver Design Center 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-14: EDO-DRAM CAS Before RAS Refresh Timing Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock period...
  • Page 79: Edo-Dram Self-Refresh Timing

    Epson Research and Development Page 73 Vancouver Design Center 7.3.3 EDO-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-15: EDO - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
  • Page 80: Fpm-Dram Read, Write, Read-Write Timing

    Page 74 Epson Research and Development Vancouver Design Center 7.3.4 FPM-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE#(read) MD(read) WE#(write) t18 t19 MD(write) Figure 7-16: FPM-DRAM Page Mode Timing Memory Clock RAS# CAS# t10 t11...
  • Page 81: Table 7-17: Fpm-Dram Read, Write, Read-Write Timing

    Epson Research and Development Page 75 Vancouver Design Center Table 7-17: FPM-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
  • Page 82: Fpm-Dram Cas Before Ras Refresh Timing

    Page 76 Epson Research and Development Vancouver Design Center 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-18: FPM-DRAM CAS Before RAS Refresh Timing Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock RAS# precharge time (REG[02Ah] bits 1-0 = 00) 2.45 t1...
  • Page 83: Fpm-Dram Self-Refresh Timing

    Epson Research and Development Page 77 Vancouver Design Center 7.3.6 FPM-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-19: FPM - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
  • Page 84: Power Sequencing

    Page 78 Epson Research and Development Vancouver Design Center 7.4 Power Sequencing 7.4.1 LCD Power Sequencing #RESET LCD Enable Bit (REG[1FCh] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Figure 7-20: LCD Panel Power-off/Power-on Timing...
  • Page 85: Power Save Mode

    Epson Research and Development Page 79 Vancouver Design Center 7.4.2 Power Save Mode Power Save Mode Enable Bit (REG[1F0h] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Memory Controller Power Save Status Bit...
  • Page 86: Table 7-21: Power Save Mode Timing

    Page 80 Epson Research and Development Vancouver Design Center Table 7-21: Power Save Mode Timing Symbol Parameter Units FPFRAME Power Save Mode Enable Bit high to FPFRAME inactive FPLINE Power Save Mode Enable Bit low to FPFRAME active FPLINE Power Save Mode Enable Bit high to FPLINE, FPSHIFT, FPDATA,...
  • Page 87: Display Interface

    Epson Research and Development Page 81 Vancouver Design Center 7.5 Display Interface 7.5.1 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPDAT[7:4] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-317 1-318...
  • Page 88: Figure 7-23: Single Monochrome 4-Bit Panel A.c. Timing

    Page 82 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-23: Single Monochrome 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 89: Table 7-22: Single Monochrome 4-Bit Panel A.c. Timing

    Epson Research and Development Page 83 Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 90: Single Monochrome 8-Bit Panel Timing

    Page 84 Epson Research and Development Vancouver Design Center 7.5.2 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-633 FPDAT6 1-10 1-634 FPDAT5...
  • Page 91: Figure 7-25: Single Monochrome 8-Bit Panel A.c. Timing

    Epson Research and Development Page 85 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 92: Table 7-23: Single Monochrome 8-Bit Panel A.c. Timing

    Page 86 Epson Research and Development Vancouver Design Center Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 93: Single Color 4-Bit Panel Timing

    Epson Research and Development Page 87 Vancouver Design Center 7.5.3 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 FPDAT[7:4] LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-G2 1-B3 1-B319 FPDAT7 1-R320...
  • Page 94: Figure 7-27: Single Color 4-Bit Panel A.c. Timing

    Page 88 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-27: Single Color 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 95: Table 7-24: Single Color 4-Bit Panel A.c. Timing

    Epson Research and Development Page 89 Vancouver Design Center Table 7-24: Single Color 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 96: Single Color 8-Bit Panel Timing (Format 1)

    Page 90 Epson Research and Development Vancouver Design Center 7.5.4 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT FPSHIFT2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12...
  • Page 97: Figure 7-29: Single Color 8-Bit Panel A.c. Timing (Format 1)

    Epson Research and Development Page 91 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 FPDAT[7:0] Figure 7-29: Single Color 8-Bit Panel A.C. Timing (Format 1) Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 98: Table 7-25: Single Color 8-Bit Panel A.c. Timing (Format 1)

    Page 92 Epson Research and Development Vancouver Design Center Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 99: Single Color 8-Bit Panel Timing (Format 2)

    Epson Research and Development Page 93 Vancouver Design Center 7.5.5 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-B3 1-G6 1-G638...
  • Page 100: Figure 7-31: Single Color 8-Bit Panel A.c. Timing (Format 2)

    Page 94 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 2) S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 101: Table 7-26: Single Color 8-Bit Panel A.c. Timing (Format 2)

    Epson Research and Development Page 95 Vancouver Design Center Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 102: Single Color 16-Bit Panel Timing

    Page 96 Epson Research and Development Vancouver Design Center 7.5.6 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE FPDAT[15:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE HNDP FPSHIFT Invalid 1-G6 1-B11 1-G635 1-R1 Invalid FPDAT15 Invalid...
  • Page 103: Figure 7-33: Single Color 16-Bit Panel A.c. Timing

    Epson Research and Development Page 97 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 7-33: Single Color 16-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 104: Table 7-27: Single Color 16-Bit Panel A.c. Timing

    Page 98 Epson Research and Development Vancouver Design Center Table 7-27: Single Color 16-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 105: Single Color 16-Bit Panel Timing With External Circuit

    Epson Research and Development Page 99 Vancouver Design Center 7.5.7 Single Color 16-Bit Panel Timing with External Circuit VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2...
  • Page 106: Figure 7-35: External Circuit For Color Single 16-Bit Panel When The Media Plug Is Enabled

    Page 100 Epson Research and Development Vancouver Design Center D[7:0] TO 16-BIT PANEL FPDAT[7:0] D[15:8] FROM S1D13506 FPSHIFT Figure 7-35: External Circuit for Color Single 16-Bit Panel When the Media Plug is Enabled Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing...
  • Page 107: Table 7-28: Single Color 16-Bit Panel (With External Circuit) A.c. Timing

    Epson Research and Development Page 101 Vancouver Design Center Table 7-28: Single Color 16-Bit Panel (with External Circuit) A.C. Timing Min. Max. Symbol Parameter Nominal Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1)
  • Page 108: Dual Monochrome 8-Bit Panel Timing

    Page 102 Epson Research and Development Vancouver Design Center 7.5.8 Dual Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)
  • Page 109: Figure 7-38: Dual Monochrome 8-Bit Panel A.c. Timing

    Epson Research and Development Page 103 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-38: Dual Monochrome 8-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 110: Table 7-29: Dual Monochrome 8-Bit Panel A.c. Timing

    Page 104 Epson Research and Development Vancouver Design Center Table 7-29: Dual Monochrome 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 111: Dual Color 8-Bit Panel Timing

    Epson Research and Development Page 105 Vancouver Design Center 7.5.9 Dual Color 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)
  • Page 112: Figure 7-40: Dual Color 8-Bit Panel A.c. Timing

    Page 106 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-40: Dual Color 8-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 113: Table 7-30: Dual Color 8-Bit Panel A.c. Timing

    Epson Research and Development Page 107 Vancouver Design Center Table 7-30: Dual Color 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 114: Dual Color 16-Bit Panel Timing

    Page 108 Epson Research and Development Vancouver Design Center 7.5.10 Dual Color 16-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)
  • Page 115: Figure 7-42: Dual Color 16-Bit Panel A.c. Timing

    Epson Research and Development Page 109 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 7-42: Dual Color 16-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 116: Table 7-31: Dual Color 16-Bit Panel A.c. Timing

    Page 110 Epson Research and Development Vancouver Design Center Table 7-31: Dual Color 16-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 117: Dual Color 16-Bit Panel Timing With External Circuit

    Epson Research and Development Page 111 Vancouver Design Center 7.5.11 Dual Color 16-Bit Panel Timing with External Circuit VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242...
  • Page 118: Figure 7-44: External Circuit For Color Dual 16-Bit Panel When The Media Plug Is Enabled

    Page 112 Epson Research and Development Vancouver Design Center UD[3:0] LD[3:0] TO 16-BIT PANEL FPDAT[7:4] UD[7:4] FPDAT[3:0] LD[7:4] FROM S1D13506 FPSHIFT Figure 7-44: External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled Sync Timing FPFRAME FPLINE...
  • Page 119: Table 7-32: Dual Color 16-Bit Panel (With External Circuit) A.c. Timing

    Epson Research and Development Page 113 Vancouver Design Center Table 7-32: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1)
  • Page 120: Tft/D-Tfd Panel Timing

    Page 114 Epson Research and Development Vancouver Design Center 7.5.12 TFT/D-TFD Panel Timing VNDP FPFRAME FPLINE LINE480 LINE1 LINE480 R[5:1], G[5:0], B[5:1] DRDY FPLINE HNDP HNDP FPSHIFT DRDY R[5:1] 1-640 G [5:0] 1-640 B[5:1] 1-640 Note: DRDY is used to indicate the first pixel...
  • Page 121: Figure 7-47: Tft/D-Tfd A.c. Timing

    Epson Research and Development Page 115 Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Figure 7-47: TFT/D-TFD A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 122: Table 7-33: Tft/D-Tfd A.c. Timing

    Page 116 Epson Research and Development Vancouver Design Center Table 7-33: TFT/D-TFD A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPSHIFT period Ts (note 1) FPSHIFT pulse width high FPSHIFT pulse width low data setup to FPSHIFT falling edge...
  • Page 123: Crt Timing

    Epson Research and Development Page 117 Vancouver Design Center 7.5.13 CRT Timing VNDP VRTC HRTC LINE480 LINE1 LINE480 RED,GREEN,BLUE HRTC HNDP HNDP 1-640 RED,GREEN,BLUE Example Timing for 640x480 CRT Figure 7-48: CRT Timing = Vertical Display Period = (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1...
  • Page 124: Table 7-34: Crt A.c. Timing

    Page 118 Epson Research and Development Vancouver Design Center VRTC HRTC Figure 7-49: CRT A.C. Timing Table 7-34: CRT A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting VRTC cycle time note 1 1152 lines VRTC pulse width low...
  • Page 125: Tv Timing

    Epson Research and Development Page 119 Vancouver Design Center 7.6 TV Timing 7.6.1 TV Output Timing The overall NTSC and PAL video timing is shown in Figure 7-50: and Figure 7-51: respec- tively. Register Programming: vertical blanking interval = 20 lines...
  • Page 126: Figure 7-51: Pal Video Timing

    Page 120 Epson Research and Development Vancouver Design Center Register Programming: vertical blanking interval = 25 lines Vertical Non-Display Period = 26 VRTC Start Position = 0 623 624 625 pre-equalizing vertical sync post-equalizing Field 1 pulse interval pulse interval...
  • Page 127: Table 7-35: Horizontal Timing For Ntsc/Pal

    Epson Research and Development Page 121 Vancouver Design Center Active Line Blanking 40 IRE Level Blanking Level Equalizing Pulse Vertical Sync Pulse Start of Horizontal Sync Figure 7-52: Horizontal Timing for NTSC/PAL Table 7-35: Horizontal Timing for NTSC/PAL Symbol Parameter...
  • Page 128: Table 7-36: Vertical Timing For Ntsc/Pal

    Page 122 Epson Research and Development Vancouver Design Center 909 (NTSC) 1134 (PAL) Vertical Vertical Non-Display Sync Period Field Vertical Odd Lines (1, 3, 5, ...) Display Period Vertical Non-Display Vertical Period Sync Even Field Vertical Even Lines (2, 4, 6, ...)
  • Page 129: Mediaplug Interface Timing

    Epson Research and Development Page 123 Vancouver Design Center 7.7 MediaPlug Interface Timing VMPCLK VMPCLKN VMPDIN[3:0] VMPCTRL VMPLCTRL VMPDout Figure 7-54: MediaPlug A.C. Timing Note The above timing diagram assumes no load. Table 7-37: MediaPlug A.C. Timing Symbol Parameter Units...
  • Page 130: Registers

    Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13506 registers. It also provides detailed information about the layout and usage of each register. 8.1 Initializing the S1D13506 Before programming the S1D13506 registers, the Register/Memory Select bit (REG[000h] bit 7) must be set.
  • Page 131: Register Descriptions

    7-2 Product Code Bits [5:0] This is a read-only register that indicates the product code of the chip. The product code for S1D13506 is 000100b. bits 1-0 Revision Code Bits [1:0] This is a read-only register that indicates the revision code of the chip. The revision code is 01b.
  • Page 132: Table 8-2: Ma[11:9]/Gpio[1:3] Pin Functionality

    Page 126 Epson Research and Development Vancouver Design Center 8.3.2 General IO Pins Registers General IO Pins Configuration Register REG[004h] GPIO3 Pin GPIO2 Pin GPIO1 Pin Reserved Reserved Reserved Reserved Reserved IO Config. IO Config. IO Config. bit 3 GPIO3 Pin IO Configuration When this bit = 1, GPIO3 is configured as an output pin.
  • Page 133 Epson Research and Development Page 127 Vancouver Design Center General IO Pins Control Register REG[008h] GPIO3 Pin GPIO2 Pin GPIO1 Pin Reserved Reserved Reserved Reserved Reserved IO Status IO Status IO Status bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low.
  • Page 134: Table 8-3: Mclk Source Select

    Page 128 Epson Research and Development Vancouver Design Center 8.3.3 MD Configuration Readback Registers MD Configuration Status Register 0 REG[00Ch] MD[7] MD[6] MD[5] MD[4] MD[3] MD[2] MD[1] MD[0] Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config.
  • Page 135: Table 8-4: Lcd Pclk Divide Selection

    Epson Research and Development Page 129 Vancouver Design Center LCD Pixel Clock Configuration Register REG[014h] LCD PCLK LCD PCLK LCD PCLK LCD PCLK Divide Select Divide Select Source Select Source Select Bit 1 Bit 0 Bit 1 Bit 0 bits 5-4...
  • Page 136: Table 8-6: Crt/Tv Pclk Divide Selection

    Page 130 Epson Research and Development Vancouver Design Center bits 5-4 CRT/TV PCLK Divide Select Bits[1:0] These bits determine the divide used to generate the CRT/TV pixel clock from the CRT/TV pixel clock source. Table 8-6: CRT/TV PCLK Divide Selection...
  • Page 137: Table 8-9: Video Clock Source Selection

    Epson Research and Development Page 131 Vancouver Design Center bits 1-0 MediaPlug Clock Source Select Bits [1:0] These bits determine the source of the MediaPlug Clock for the MediaPlug Interface. See Section 7.7, “MediaPlug Interface Timing” on page 123 for AC Timing.
  • Page 138: Table 8-11: Memory Type Selection

    Page 132 Epson Research and Development Vancouver Design Center 8.3.5 Memory Configuration Registers Memory Configuration Register REG[020h] Memory Type Memory Type Bit 1 Bit 0 bits 1-0 Memory Type Bits [1:0] These bits specify the memory type. Table 8-11: Memory Type Selection...
  • Page 139: Table 8-13: Dram Refresh Rate Selection

    Epson Research and Development Page 133 Vancouver Design Center bits 2-0 DRAM Refresh Rate Select Bits [2:0] These bits specify the divide used to generate the DRAM refresh clock rate, which is equal (ValueOfTheseBits + 6) to 2 , from the MCLK source (either BUSCLK or CLKI as determined by REG[010h] bit 0).
  • Page 140: Table 8-14: Dram Timing Control Selection

    Page 134 Epson Research and Development Vancouver Design Center DRAM Timing Control Register 0 REG[02Ah] DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing Control Control Control Control Control Control Control Control Register...
  • Page 141: Table 8-15: Panel Data Width Selection

    When this bit = 1, the EL Panel support circuit is enabled. When this bit = 0, there is no hardware effect. This bit enables the S1D13506 built-in circuit for EL panels which require the Frame Rate Modulation (FRM) to remain static for one frame after every 262143 frames (approxi- mately 1 hour at 60Hz refresh).
  • Page 142: Table 8-16: Horizontal Display Width (Pixels)

    Page 136 Epson Research and Development Vancouver Design Center MOD Rate Register REG[031h] MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit bits 5-0 MOD Rate Bits [5:0] For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal (DRDY).
  • Page 143 Epson Research and Development Page 137 Vancouver Design Center LCD Horizontal Non-Display Period Register REG[034h] Horizontal Horizontal Horizontal Horizontal Horizontal Non-Display Non-Display Non-Display Non-Display Non-Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0...
  • Page 144: Table 8-17: Lcd Fpline Polarity Selection

    Page 138 Epson Research and Development Vancouver Design Center TFT FPLINE Pulse Width Register REG[036h] LCD FPLINE TFT FPLINE TFT FPLINE TFT FPLINE TFT FPLINE Polarity Pulse Width Pulse Width Pulse Width Pulse Width Select Bit 3 Bit 2 Bit 1...
  • Page 145 Epson Research and Development Page 139 Vancouver Design Center LCD Vertical Non-Display Period Register REG[03Ah] LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Period Status Period Bit 5...
  • Page 146: Table 8-18: Lcd Fpframe Polarity Selection

    Page 140 Epson Research and Development Vancouver Design Center TFT FPFRAME Pulse Width Register REG[03Ch] FPFRAME FPFRAME FPFRAME FPFRAME Polarity Pulse Width Pulse Width Pulse Width Select Bit 2 Bit 1 Bit 0 bit 7 LCD FPFRAME Polarity Select This bit selects the polarity of FPFRAME for all LCD panels.
  • Page 147: Table 8-19: Setting Swivelview Modes

    Epson Research and Development Page 141 Vancouver Design Center bit 4 SwivelView™ Enable Bit 1 When this bit = 1, the LCD display image is rotated 180° clockwise. Please refer to Section 15, “SwivelView™” on page 200 for application and limitations.
  • Page 148 RGB component which results in 256K colors per pixel (64x64x64). For the S1D13506, 16 bpp is arranged as 5-6-5 RGB. In this mode, when dithering is enabled, the LUT is bypassed and the original 16-bit data is used as a pointer into the 64 shades per color in the following manner.
  • Page 149 Epson Research and Development Page 143 Vancouver Design Center LCD Display Start Address Register 0 REG[042h] LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display Start Address Start Address Start Address Start Address...
  • Page 150: Table 8-21: Lcd Pixel Panning Selection

    Page 144 Epson Research and Development Vancouver Design Center LCD Pixel Panning Register REG[048h] LCD Pixel LCD Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 bits 3-2 Reserved. Must be set to 0. bits 1-0 LCD Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the LCD display.
  • Page 151: Crt/Tv Configuration Registers

    Epson Research and Development Page 145 Vancouver Design Center LCD Display FIFO Low Threshold Control Register REG[04Bh] LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display FIFO Low FIFO Low FIFO Low FIFO Low FIFO Low FIFO Low...
  • Page 152 Page 146 Epson Research and Development Vancouver Design Center CRT/TV HRTC Start Position Register REG[053h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV HRTC Start HRTC Start HRTC Start HRTC Start HRTC Start HRTC Start Position Bit 5 Position Bit 4 Position Bit 3...
  • Page 153 Epson Research and Development Page 147 Vancouver Design Center CRT/TV Vertical Display Height Register 0 REG[056h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display...
  • Page 154 Page 148 Epson Research and Development Vancouver Design Center CRT/TV VRTC Start Position Register REG[059h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start Position Bit 6 Position Bit 5...
  • Page 155: Table 8-22: Dac Output Level Selection

    Epson Research and Development Page 149 Vancouver Design Center CRT/TV Output Control Register REG[05Bh] TV S-Video/ DAC Output Chrominance Luminance Composite PAL/NTSC Level Select Filter Enable Filter Enable Output Select Output Select bit 5 TV Chrominance Filter Enable When this bit = 1, the TV chrominance filter is enabled.
  • Page 156: Table 8-23: Crt/Tv Bit-Per-Pixel Selection

    Page 150 Epson Research and Development Vancouver Design Center 8.3.9 CRT/TV Display Mode Registers CRT/TV Display Mode Register REG[060h] CRT/TV Bit- CRT/TV Bit- CRT/TV Bit- CRT/TV per-pixel per-pixel per-pixel Display Blank Select Bit 2 Select Bit 1 Select Bit 0...
  • Page 157 Epson Research and Development Page 151 Vancouver Design Center CRT/TV Display Start Address Register 0 REG[062h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Display Start Display Start Display Start Display Start Display Start Display Start Display Start Display Start...
  • Page 158: Table 8-24: Crt/Tv Pixel Panning Selection

    Page 152 Epson Research and Development Vancouver Design Center CRT/TV Pixel Panning Register REG[068h] CRT/TV Pixel CRT/TV Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 bits 3-2 Reserved. Must be set to 0. bits 1-0 CRT/TV Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the CRT/TV display.
  • Page 159: Table 8-25: Lcd Ink/Cursor Selection

    Epson Research and Development Page 153 Vancouver Design Center CRT/TV Display FIFO Low Threshold Control Register REG[06Bh] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Threshold Threshold Threshold Threshold Threshold...
  • Page 160: Table 8-26: Lcd Ink/Cursor Start Address Encoding

    Page 154 Epson Research and Development Vancouver Design Center LCD Ink/Cursor Start Address Register REG[071h] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7...
  • Page 161 Epson Research and Development Page 155 Vancouver Design Center LCD Cursor Y Position Register 0 REG[074h] LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y...
  • Page 162 Page 156 Epson Research and Development Vancouver Design Center LCD Ink/Cursor Red Color 0 Register REG[078h] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Red Color 0 Red Color 0 Red Color 0 Red Color 0 Red Color 0 Bit 4 Bit 3...
  • Page 163: Table 8-27: Crt/Tv Ink/Cursor Selection

    Epson Research and Development Page 157 Vancouver Design Center LCD Ink/Cursor FIFO High Threshold Register REG[07Eh] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor FIFO High FIFO High FIFO High FIFO High Threshold Threshold Threshold Threshold Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 164: Table 8-28: Crt/Tv Ink/Cursor Start Address Encoding

    Page 158 Epson Research and Development Vancouver Design Center CRT/TV Ink/Cursor Start Address Register REG[081h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address...
  • Page 165 Epson Research and Development Page 159 Vancouver Design Center REG[082h] bits 7-0 CRT/TV Cursor X Position Bits [9:0] REG[083h] bits 1-0 A 10-bit register that defines the horizontal position of the CRT/TV Cursor’s top left hand corner in pixel units. This register is only valid when Cursor has been selected in the CRT/TV Ink/Cursor select registers.
  • Page 166 Page 160 Epson Research and Development Vancouver Design Center CRT/TV Ink/Cursor Green Color 0 Register REG[087h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 0 Green Color 0 Green Color 0 Green Color 0...
  • Page 167: Table 8-29: Bitblt Active Status

    Epson Research and Development Page 161 Vancouver Design Center CRT/TV Ink/Cursor FIFO High Threshold Register REG[08Eh] CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor FIFO High FIFO High FIFO High FIFO High Threshold Threshold Threshold Threshold Bit 3 Bit 2...
  • Page 168: Table 8-30: Bitblt Fifo Data Available

    Page 162 Epson Research and Development Vancouver Design Center bit 6 BitBLT FIFO Not-Empty Status This is a read-only status bit. When this bit = 1, the BitBLT FiFO has at least one data. When this bit = 0, the BitBLT FIFO is empty.
  • Page 169: Table 8-31: Bitblt Rop Code/Color Expansion Function Selection

    Epson Research and Development Page 163 Vancouver Design Center BitBLT Control Register 1 REG[101h] BitBLT Color Reserved Format Select bit 4 Reserved. Must be set to 0. bit 0 BitBLT Color Format Select This bit selects the color format that the 2D operation is applied to.
  • Page 170: Table 8-32: Bitblt Operation Selection

    Page 164 Epson Research and Development Vancouver Design Center BitBLT Operation Register REG[103h] BitBLT BitBLT BitBLT BitBLT Operation Operation Operation Operation Bit 3 Bit 2 Bit 1 Bit 0 bits 3-0 BitBLT Operation Bits [3:0] Specifies the 2D Operation to be carried out based on the following table:...
  • Page 171: Table 8-33: Bitblt Source Start Address Selection

    Epson Research and Development Page 165 Vancouver Design Center BitBLT Source Start Address Register 0 REG[104h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Source Start Source Start Source Start Source Start Source Start Source Start Source Start Source Start...
  • Page 172 Page 166 Epson Research and Development Vancouver Design Center BitBLT Destination Start Address Register 0 REG[108h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Destination Destination Destination Destination Destination Destination Destination Destination Start Address Start Address Start Address Start Address...
  • Page 173 Epson Research and Development Page 167 Vancouver Design Center BitBLT Width Register 0 REG[110h] BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
  • Page 174 Page 168 Epson Research and Development Vancouver Design Center BitBLT Background Color Register 0 REG[114h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Background Background Background Background Background Background Background Background Color Color Color Color Color Color Color Color Bit 7...
  • Page 175: Table 8-34: Lut Mode Selection

    7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13506 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 12, “Look-Up Table Architecture” on page 185 for details.
  • Page 176: Power Save Configuration Registers

    Page 170 Epson Research and Development Vancouver Design Center Look-Up Table Data Register REG[1E4h] LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit 0 bits 7-4 LUT Data Bits [3:0] This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the pointer controlled by the Look-Up Table Address Register (REG[1E2h]).
  • Page 177: Miscellaneous Registers

    Epson Research and Development Page 171 Vancouver Design Center bit 0 Memory Controller Power Save Status This bit indicates the power save state of the memory controller. When this bit = 1, the memory controller is powered down and is either in self refresh or no refresh mode.
  • Page 178: Table 8-35: Setting Swivelview Modes

    Page 172 Epson Research and Development Vancouver Design Center 8.3.16 Common Display Mode Register Display Mode Register REG[1FCh] SwivelView™ Display Mode Display Mode Display Mode Enable Bit 0 Select Bit 2 Select Bit 1 Select Bit 0 bit 6 SwivelView™ Enable Bit 0 When this bit = 1, the LCD and CRT display image is rotated 90°...
  • Page 179: Table 8-37: Mediaplug Lcmd Read/Write Descriptions

    Vancouver Design Center 8.3.17 MediaPlug Register Descriptions The S1D13506 has built-in support for Winnov’s MediaPlug connection designed for video cameras. The following registers are used to control the connection and accept data from the camera. The MediaPlug registers decode A11-A0 and require A20 = 0 and A12 = 1. The MediaPlug registers are 16-bit wide.
  • Page 180: Table 8-39: Cable Detect And Remote Powered Status

    Page 174 Epson Research and Development Vancouver Design Center bit 7 Cable Detected Status (MediaPlug Parameter Rstat) The cable detected status as determined by the MPD(1) pin. When this bit = 0, a MediaPlug cable is connected. When this bit = 1, a MediaPlug cable is not detected.
  • Page 181: Table 8-40: Mediaplug Cmd Read/Write Descriptions

    Epson Research and Development Page 175 Vancouver Design Center MediaPlug Reserved LCMD Register REG[1002h] LCMD Bit 23 LCMD Bit 22 LCMD Bit 21 LCMD Bit 20 LCMD Bit 19 LCMD Bit 18 LCMD Bit 17 LCMD Bit 16 LCMD Bit 31...
  • Page 182: Table 8-41: Mediaplug Commands

    Page 176 Epson Research and Development Vancouver Design Center bit 2-0 Command Field (MediaPlug Parameter C) Selects the command as follows: Table 8-41: MediaPlug Commands Command Field Command [bits 2:0] Remote-Reset: Hardware reset of remote. Stream-End: Indicates end of data streaming operation.
  • Page 183: Bitblt Data Registers Descriptions

    Epson Research and Development Page 177 Vancouver Design Center 8.3.18 BitBLT Data Registers Descriptions The BitBLT data registers decode A19-A0 and require A20 = 1. The BitBLT data registers are 16-bit wide. Byte access to the BitBLT data registers is not allowed.
  • Page 184: D Bitblt Engine

    Epson Research and Development Vancouver Design Center 9 2D BitBLT Engine The S1D13506 has a built-in 2D BitBLT engine which increases the performance of Bit Block Transfers (BitBLT). This section will discuss the BitBLT engine design and functionality. 9.1 Functional Description The 2D BitBLT engine is designed using a 16-bit architecture.
  • Page 185 Epson Research and Development Page 179 Vancouver Design Center Pattern Fill The Pattern Fill BitBLT fills a specified BitBLT area with an 8 pixel by 8 line pattern in full color defined in off-screen display buffer. The pattern data has to be stored in a contiguous address (i.e.
  • Page 186 Page 180 Epson Research and Development Vancouver Design Center Transparent Move BitBLT The Transparent Move BitBLT supports bit block transfers from display buffer to display buffer in positive direction only. When the source color is equal to key color, which is defined in Background Color Register, the destination area is not updated.
  • Page 187: Table 10-1: S1D13506 Addressing

    The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below: Table 10-1: S1D13506 Addressing M/R# Access Register access - see Section 8.2, “Register Mapping”...
  • Page 188: Image Buffer

    Page 182 Epson Research and Development Vancouver Design Center 10.1 Image Buffer The image buffer contains the formatted display mode data – see Section 11.1, “Display Mode Data Format” on page 183. The displayed image(s) may occupy only a portion of this space; the remaining area may be used for multiple images –...
  • Page 189: Display Configuration

    Epson Research and Development Page 183 Vancouver Design Center 11 Display Configuration 11.1 Display Mode Data Format The following diagrams show the display mode data formats for a little endian system: 4 bpp: bit 7 bit 0 Byte 0 Byte 1...
  • Page 190: Figure 11-2: Image Manipulation

    LCD display. The screen image on the CRT/TV is manipulated similarly. When EISD is enabled (see Section 16, “EPSON Independent Simultaneous Display (EISD)” on page 209), the images on the LCD and on the CRT/TV are independent of each other.
  • Page 191: Figure 12-1: 4 Bit-Per-Pixel Monochrome Mode Data Output Path

    Epson Research and Development Page 185 Vancouver Design Center 12 Look-Up Table Architecture The following depictions are intended to show the display data output path only. 12.1 Monochrome Modes The green LUT is used for all monochrome modes. 4 Bit-Per-Pixel Monochrome Mode...
  • Page 192: Figure 12-2: 4 Bit-Per-Pixel Color Mode Data Output Path

    Page 186 Epson Research and Development Vancouver Design Center 12.2 Color Modes 4 Bit-Per-Pixel Color Red Look-Up Table 256x4 0000 0001 0010 0011 0100 0101 0110 4-bit Red Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 Green Look-Up Table 256x4...
  • Page 193: Figure 12-3: 8 Bit-Per-Pixel Color Mode Data Output Path

    Epson Research and Development Page 187 Vancouver Design Center 8 Bit-Per-Pixel Color Red Look-Up Table 256x4 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Red Data 1111 1000 1111 1001 1111 1010...
  • Page 194: Table 13-1: Required Clock Frequencies For Ntsc/Pal

    Page 188 Epson Research and Development Vancouver Design Center 13 TV Considerations 13.1 NTSC/PAL Operation NTSC or PAL video is supported in either composite or S-video format. Filters may be enabled to reduce the distortion associated with displaying high resolution computer images on an interlaced TV display.
  • Page 195: Filters

    Epson Research and Development Page 189 Vancouver Design Center 13.3 Filters When displaying computer images on a TV, several image distortions are likely to arise: • cross-luminance distortion. • cross-chrominance distortion. • flickering. These distortions are caused by the high-resolution nature of computer images which typically contain sharp color transitions, and sharp luminance transitions (e.g., high...
  • Page 196: Table 13-2: Ntsc/Pal Svideo-Y (Luminance) Output Levels

    Page 190 Epson Research and Development Vancouver Design Center 13.4 TV Output Levels white yellow cyan green magenta blue black blank sync Figure 13-1: NTSC/PAL SVideo-Y (Luminance) Output Levels Table 13-2: NTSC/PAL SVideo-Y (Luminance) Output Levels NTSC / PAL NTSC / PAL...
  • Page 197: Table 13-3: Ntsc/Pal Svideo-C (Chrominance) Output Levels

    Epson Research and Development Page 191 Vancouver Design Center cyan green magenta blue yellow burst blanking burst yellow blue green magenta cyan Figure 13-2: NTSC/PAL SVideo-C (Chrominance) Output Levels Table 13-3: NTSC/PAL SVideo-C (Chrominance) Output Levels NTSC / PAL NTSC / PAL...
  • Page 198: Table 13-4: Ntsc/Pal Composite Output Levels

    Page 192 Epson Research and Development Vancouver Design Center cyan yellow green white yellow magenta cyan green yellow magenta blue burst blue cyan black blank green magenta burst sync blue Figure 13-3: NTSC/PAL Composite Output Levels Table 13-4: NTSC/PAL Composite Output Levels...
  • Page 199: Table 13-5: Minimum And Maximum Values For Ntsc/Pal

    Epson Research and Development Page 193 Vancouver Design Center 13.5 TV Image Display and Positioning This section describes how to setup and position an image to be displayed on a TV. Figure 13-4: “NTSC/PAL Image Positioning,” on page 194 shows an image positioned on the TV display with the related programmable parameters.
  • Page 200: Figure 13-4: Ntsc/Pal Image Positioning

    Page 194 Epson Research and Development Vancouver Design Center Vertical Sync Field 1, 3 Image t4 / 2 Odd Lines (1, 3, 5, ...) Vertical t5 + 1T Sync LINE Even Field 2, 4 Even Lines (2, 4, 6, ...)
  • Page 201: Table 13-6: Register Values For Example Ntsc/Pal Images

    Epson Research and Development Page 195 Vancouver Design Center Total Display Total Display 752 x 484 920 x 572 Visible Display Visible Display 696 x 436 856 x 518 NTSC Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL Note For most implementations, the visible display does not equal the total display.
  • Page 202: Table 14-1: Ink/Cursor Start Address Encoding

    Page 196 Epson Research and Development Vancouver Design Center 14 Ink Layer/Hardware Cursor Architecture 14.1 Ink Layer/Hardware Cursor Buffers The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There may be several Ink Layer/Hardware Cursor images stored in the display buffer but only one may be active at any given time.
  • Page 203: Table 14-2: Ink/Cursor Color Select

    Epson Research and Development Page 197 Vancouver Design Center 14.2 Ink/Cursor Data Format The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the Ink/Cursor data format for a little endian system. 2-bpp: bit 7 bit 0 Byte 0...
  • Page 204: Figure 14-2: Unclipped Cursor Positioning

    Page 198 Epson Research and Development Vancouver Design Center 14.3 Ink/Cursor Image Manipulation 14.3.1 Ink Image The Ink image should always start at the top left pixel, i.e. Cursor X Position and Cursor Y Position registers should always be set to zero. The width and height of the ink image are automatically calculated to completely cover the display.
  • Page 205: Figure 14-3: Clipped Cursor Positioning

    Epson Research and Development Page 199 Vancouver Design Center P(-x;-y) P(0;0) P(63-x;63-y) Figure 14-3: Clipped Cursor Positioning where For LCD: x = (REG[073h] bits [1:0], REG[072h]) <= 63 and REG[073h] bit 7 = 1 y = (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit 7 = 1 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit 7 = 1...
  • Page 206: Concept

    90° SwivelView™. The display is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13506 in the following sense: A–B–C–D. The S1D13506 rotates and stores the application image in the following sense: C–A–D–B, the same sense as display refresh.
  • Page 207: Figure 15-1: Relationship Between Screen Image And 90° Rotated Image In The Display Buffer

    Epson Research and Development Page 201 Vancouver Design Center 1024 pixels 1024 pixels display start address portrait window Rotated image in the display buffer Image seen by the user Figure 15-1: Relationship Between Screen Image and 90° Rotated Image in the Display Buffer...
  • Page 208 Page 202 Epson Research and Development Vancouver Design Center LCD/CRT Memory Address Offset (words) = 1024 for 15/16 bpp mode = 512 for 8 bpp mode Display Start Address As seen in Figure 15-1: “Relationship Between Screen Image and 90° Rotated Image in the Display Buffer,”...
  • Page 209: Physical Memory Requirement

    The following table summarizes the DRAM size requirement for 90° SwivelView™ for different panel sizes and display modes. Note that DRAM size for the S1D13506 is limited to either 512K byte or 2M byte. The calculation is based on the minimum required image buffer size and the Dual Panel Buffer size.
  • Page 210: Table 15-1: Minimum Dram Size Required For Swivelview

    Page 204 Epson Research and Development Vancouver Design Center Table 15-1: Minimum DRAM Size Required for SwivelView™ Display Min. Image Dual Panel Minimum Ink/Cursor Ink/Cursor Panel Size Panel Type Mode Buffer Size Buffer Size DRAM Size Buffer Size Location 8 bpp...
  • Page 211: Register Programming

    Epson Research and Development Page 205 Vancouver Design Center 15.3 180° SwivelView™ 180° SwivelView™ is accomplished by fetching the display buffer image in the reverse address direction, starting at the bottom-right corner of the image. Unlike 90° SwivelView™, the 180° SwivelView™ image is not rotated in the display buffer. The image is simply displayed 180°...
  • Page 212: Limitations

    Page 206 Epson Research and Development Vancouver Design Center 15.3.2 Limitations The following limitations apply to 180° SwivelView™: • Hardware Cursor and Ink Layer images are not rotated – software rotation must be used. • CRT/TV mode is not supported.
  • Page 213: Physical Memory Requirement

    Epson Research and Development Page 207 Vancouver Design Center Display Start Address The Display Start Address must be programmed to be at the bottom-right corner of the image, since the display is now refreshed in the reverse direction. The LCD Display Start Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly.
  • Page 214: Limitations

    Page 208 Epson Research and Development Vancouver Design Center 15.4.3 Limitations The following limitations apply to 270° SwivelView™: • Only 8/15/16 bpp modes are supported – 4 bpp mode is not supported. • Hardware Cursor and Ink Layer images are not rotated – software rotation must be used.
  • Page 215: Introduction

    16 EPSON Independent Simultaneous Display (EISD) 16.1 Introduction EPSON Independent Simultaneous Display (EISD) allows the S1D13506 to display independent images on two different displays (LCD panel and CRT or TV). The LCD panel timings and mode setup are programmed through the Panel Configuration Registers (REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]).
  • Page 216: Bandwidth Limitation

    When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth available to the S1D13506. The result is that display modes with a high resolution or color depth may not be supported. In some cases, Ink Layers may not be possible on one or both of the displays.
  • Page 217: Table 17-1: Mediaplug Interface Pin Mapping

    Page 211 Vancouver Design Center 17 MediaPlug Interface Winnov's MediaPlug Slave interface has been incorporated into the S1D13506. The MediaPlug Slave follows the Specification For Winnov MediaPlug Slave, Local module, Document Rev 0.3 with the following exceptions. 17.1 Revision Code The MediaPlug Slave Revision Code can be determined by reading bits 11:8 of the LCMD register.
  • Page 218: Clocking

    Page 212 Epson Research and Development Vancouver Design Center 18 Clocking 18.1 Frame Rate Calculation 18.1.1 LCD Frame Rate Calculation The maximum LCD frame rate is calculated using the following formula. LCD PCLK max. LCD Frame Rate --------------------------------------------------------------------------------------------------------- - ...
  • Page 219: Crt Frame Rate Calculation

    Epson Research and Development Page 213 Vancouver Design Center 18.1.2 CRT Frame Rate Calculation The maximum CRT frame rate is calculated using the following formula. CRT PCLK max. CRT Frame Rate --------------------------------------------------------------------------------------------------------- - × CHDP CHNDP CVDP CVNDP Where: CRT PCLKmax= maximum CRT pixel clock frequency...
  • Page 220: Tv Frame Rate Calculation

    Page 214 Epson Research and Development Vancouver Design Center 18.1.3 TV Frame Rate Calculation The maximum TV frame rate is calculated using the following formula. TV PCLK max. TV Frame Rate ---------------------------------------------------------------------------------------------------------------------- - × THDP THNDP TVDP TVNDP Where: TV PCLKmax= maximum TV pixel clock frequency...
  • Page 221: Example Frame Rates

    Epson Research and Development Page 215 Vancouver Design Center 18.2 Example Frame Rates For all example frame rates the following conditions apply: • Dual panel buffer is enabled for dual panel. • TV flicker filter is enabled for TV. • MCLK is 40MHz.
  • Page 222: Table 18-2: Frame Rates For 800X600 With Eisd Disabled

    Page 216 Epson Research and Development Vancouver Design Center Table 18-1: Frame Rates for 640x480 with EISD Disabled (Continued) Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP VNDP Frame LCD Type PCLK HNDP VNDP Rate Rate (lines) (MHz) (pixels) (MHz)
  • Page 223: Table 18-3: Frame Rates For Lcd And Crt (640X480) With Eisd Enabled

    Epson Research and Development Page 217 Vancouver Design Center 18.2.3 Frame Rates for LCD and CRT (640x480) with EISD Enabled Table 18-3: Frame Rates for LCD and CRT (640x480) with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK( HNDP...
  • Page 224: Table 18-4: Frame Rates For Lcd And Crt (800X600) With Eisd Enabled

    Page 218 Epson Research and Development Vancouver Design Center 18.2.4 Frame Rates for LCD and CRT (800x600) with EISD Enabled Table 18-4: Frame Rates for LCD and CRT (800x600) with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...
  • Page 225: Table 18-5: Frame Rates For Lcd And Ntsc Tv With Eisd Enabled

    Epson Research and Development Page 219 Vancouver Design Center 18.2.5 Frame Rates for LCD and NTSC TV with EISD Enabled Table 18-5: Frame Rates for LCD and NTSC TV with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...
  • Page 226: Table 18-6: Frame Rates For Lcd And Pal Tv With Eisd Enabled

    Page 220 Epson Research and Development Vancouver Design Center 18.2.6 Frame Rates for LCD and PAL TV with EISD Enabled Table 18-6: Frame Rates for LCD and PAL TV with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...
  • Page 227: Power Save Mode

    Additionally, the S1D13506 has a software initiated power save mode. 19.1 Display Modes The S1D13506 resets with both displays inactive, i.e. neither the LCD nor CRT/TV pipelines are active. The displays are independently enabled/disabled by REG[1FCh] bits 2-0: the CRT/TV is instantaneously enabled/disabled by these bits; the LCD is powered up/down according to the sequences in Section 7.4, “Power Sequencing”...
  • Page 228: Table 19-1: Power Save Mode Summary

    Page 222 Epson Research and Development Vancouver Design Center 19.4 Power Save Mode Summary Table 19-1: Power Save Mode Summary Power Save Mode Function LCD Disabled CRT/TV Disabled Enabled LCD Display Active? CRT/TV Display Active? Register Access Possible? Memory Access Possible?
  • Page 229: Figure 20-1: Clock Selection

    Epson Research and Development Page 223 Vancouver Design Center 20 Clocks 20.1 Clock Selection The following diagram provides a logical representation of the S1D13506 internal clocks. CLKI BUSCLK BCLK CLKI2 ÷2 MD12 at RESET# MCLK ÷2 REG[010h] bit 0 REG[010h] bit 4 ÷2...
  • Page 230: Clock Descriptions

    Vancouver Design Center 20.2 Clock Descriptions 20.2.1 MCLK MCLK should be configured as close to its maximum (40MHz) as possible. The S1D13506 contains sophisticated clock management, therefore, very little power is saved by reducing the MCLK frequency. The frequency of MCLK is directly proportional to the bandwidth of the video memory.
  • Page 231: Table 20-1: Clocks Vs. Functions

    Vancouver Design Center 20.3 Clocks vs. Functions The S1D13506 has five clock signals. Not all clock signals must be active for certain chip functions to be carried out. The following table shows which clocks are required for each chip function.
  • Page 232: Figure 21-1: Mechanical Drawing Qfp15

    Page 226 Epson Research and Development Vancouver Design Center 21 Mechanical Data Unit: mm 128-pin QFP15 surface mount package 16.0 ± 0.4 14.0 ± 0.1 Index 0.16 ± 0.1 0~10° 0.5 ± 0.2 Figure 21-1: Mechanical Drawing QFP15 S1D13506 Hardware Functional Specification...
  • Page 233: Sales And Technical Support

    Epson Research and Development Page 227 Vancouver Design Center 22 Sales and Technical Support Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd. 421-8, Hino, Hino-shi San Jose, CA 95134, USA 10F, No.
  • Page 234 Page 228 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 235: Programming Notes And Examples

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 236 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...
  • Page 237 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........11 Initialization .
  • Page 238 SwivelView™ ........56 S1D13506 SwivelView ......56 Registers .
  • Page 239 12.2 Considerations ......100 13 Identifying the S1D13506 ....... . 101 14 Hardware Abstraction Layer (HAL) .
  • Page 240 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...
  • Page 241 List of Tables Table 2-1: S1D13506 Initialization Sequence ......12 Table 4-1: Look-Up Table Configurations ......20 Table 4-2: Suggested LUT Values to Simulate VGA Default 16 Color Palette .
  • Page 242 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...
  • Page 243 Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Pixel Storage for 4 Bpp in One Byte of Display Buffer ....16 Figure 3-2: Pixel Storage for 8 Bpp in One Byte of Display Buffer .
  • Page 244 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...
  • Page 245 This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to simplify the programming of the S1D13506. Most S1D1350x and S1D1370x products have HAL support, thus allowing OEMs to do multiple designs with a common code base.
  • Page 246 2 Initialization This section describes how to initialize the S1D13506. Sample code for performing initial- ization of the S1D13506 is provided in the file init13506.c which is available on the internet at www.eea.epson.com. S1D13506 initialization can be broken into three steps.
  • Page 247 Epson Research and Development Page 13 Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also Program the Frame Buffer Memory Configuration [020h] 0000 0000 Registers. [021h] 0000 0110 see REG[020h] - REG[02Bh] for details [02Ah]...
  • Page 248 Page 14 Epson Research and Development Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also [060h] 0000 0000 Program the CRT/TV Display Output Format and Configuration Registers including the FIFOs. [062h] 0000 0000 [063h] 0000 0000 For this example, these values are = don’t care.
  • Page 249 Epson Research and Development Page 15 Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also [100h] 0000 0000 Program the 2D acceleration (BitBLT) registers to a known state. [101h] 0000 0000 [102h] 0000 0000 [103h]...
  • Page 250: Memory Models

    3.1 Display Buffer Location The S1D13506 supports either a 512k byte or 2M byte display buffer. The display buffer is memory mapped and is accessible directly by software. The memory block location assigned to the S1D13506 display buffer varies with each individual hardware platform.
  • Page 251: Memory Organization For 8 Bpp (256 Colors/16 Gray Shades)

    Figure 3-3: Pixel Storage for 15 Bpp in Two Bytes of Display Buffer At a color depth of 15 bpp the S1D13506 is capable of displaying 32768 colors. The 32768 color pixel is divided into four parts: one reserved bit, five bits for red, five bits for green, and five bits for blue.
  • Page 252: Memory Organization For 16 Bpp (65536 Colors/64 Gray Shades)

    Figure 3-4: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At a color depth of 16 bpp the S1D13506 is capable of displaying 65536 colors. The 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue.
  • Page 253: Look-Up Table (Lut)

    For a discussion of the LUT architecture, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. The S1D13506 is designed with a separate LUT for both the LCD and CRT/TV. Each LUT consists of 256 indexed red/green/blue entries. Each LUT entry is four bits wide. The color depth determines how many indices are used to output the image to the display.
  • Page 254: Look-Up Table Organization

    This intensity can range in value between 0 and 0Fh. • The S1D13506 Look-Up Table is linear. This means increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh in the red bank results in bright red output while a LUT entry of 05h results in dull red.
  • Page 255: Color Modes

    4 bpp color When the S1D13506 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT.
  • Page 256 VGA RAMDAC and the S1D13506 LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT level 1...). Additionally, the significant bits of the color tables are located at different offsets within their respective bytes.
  • Page 257 Epson Research and Development Page 23 Vancouver Design Center Table 4-3: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) Index Index Index Index 15 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not required.
  • Page 258: Gray Shade Modes

    Page 24 Epson Research and Development Vancouver Design Center 4.2.2 Gray Shade Modes This discussion of gray shade (monochrome) modes only applies to the panel interface. Monochrome mode is selected when REG[030h] bit 2 returns a 0. In this mode the value output to the panel is derived solely from the green component of the LUT.
  • Page 259 Epson Research and Development Page 25 Vancouver Design Center 8 bpp gray shade The 8 bpp gray shade mode uses the green component of the first 16 LUT entries. The green portion of the LUT provides 16 possible intensities. There is no increase in gray shades when selecting 8 bpp mode over 4 bpp mode;...
  • Page 260: Virtual Displays

    Page 26 Epson Research and Development Vancouver Design Center 5 Virtual Displays This section discusses the concept of a virtual display and covers navigation within a virtual display using panning and scrolling. 5.1 Virtual Display Virtual display is where the image to be viewed is larger than the physical display. This can be in the horizontal, vertical or both dimensions.
  • Page 261: Registers

    Epson Research and Development Page 27 Vancouver Design Center 5.1.1 Registers REG[046h] LCD Memory Address Offset Register 0 LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory Address Address Address Address Address Address...
  • Page 262: Examples

    “virtual” image. After determining the amount of memory used by each line (see example 1), calculate whether there is enough memory to support the desired number of lines. 1. Initialize the S1D13506 registers for a 640x480 panel. (See Section 2, “Initialization” on page 12). 2. Calculate the number of pixels per word.
  • Page 263 Epson Research and Development Page 29 Vancouver Design Center = PixelsPerVirtualLine ÷ PixelsPerWord Offset = 800 ÷ 4 = 200 words = 0C8h words For the LCD, REG[047h] is set to 00h and REG[046h] is set to C8h. For the CRT/TV, REG[067h] is set to 00h and REG[066h] is set to C8h.
  • Page 264: Panning And Scrolling

    The pixel pan registers (REG[048h] for LCD, REG[068h] for CRT/TV) allow panning in smaller increments than changing the start address alone. Internally, the S1D13506 latches different signals at different times. Due to this internal sequence, the start address and pixel pan registers should be accessed in a specific order during panning and scrolling operations, in order to provide the smoothest scrolling.
  • Page 265: Registers

    Epson Research and Development Page 31 Vancouver Design Center 5.2.1 Registers REG[042h] LCD Display Start Address Register 0 LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display Start Address Start Address Start Address...
  • Page 266 Page 32 Epson Research and Development Vancouver Design Center REG[048h] LCD Pixel Panning Register LCD Pixel LCD Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 REG[068h] CRT/TV Pixel Panning Register CRT/TV Pixel CRT/TV Pixel Reserved Reserved Panning Bit 1...
  • Page 267: Examples

    Epson Research and Development Page 33 Vancouver Design Center When panning to the left on an LCD set for a color depth of 4 bpp, the registers would be updated as follows. 1. Pan left by 1 pixel - decrement the pixel panning register by 1: REG[048h] = 11b.
  • Page 268 Page 34 Epson Research and Development Vancouver Design Center StartAddress = PanValue SHR 2 (remove PixelPan bits) 3. Write the pixel panning and start address register values using the procedure outlined in Section 5.2.1, “Registers” on page 31. Example 4: Scrolling - Up and Down...
  • Page 269: Power Save Mode

    6 Power Save Mode The S1D13506 has been designed for very low-power applications. During normal operation, the internal clocks are dynamically disabled when not required. The S1D13506 design also includes a Power Save Mode to further save power. When Power Save Mode is initiated, automatic LCD power sequencing takes place to ensure the LCD bias power supply is disabled properly.
  • Page 270: Power Save Status Bits

    The Memory Controller Power Save Status bit is a read-only status bit which indicates the power save state of the S1D13506 DRAM interface. When this bit returns a 1, the DRAM interface is powered down (the DRAM is either in self-refresh mode or completely idle).
  • Page 271: Dram Refresh Selection

    Epson Research and Development Page 37 Vancouver Design Center 6.2.3 DRAM Refresh Selection REG[021h] DRAM Refresh Rate Register DRAM DRAM DRAM Refresh Refresh Refresh Rate Refresh Rate Refresh Rate Select Bit 1 Select Bit 0 Bit 2 Bit 1 Bit 0 The Refresh Select bits specify the type of DRAM refresh used while Power Save Mode is enabled.
  • Page 272: Lcd Power Sequencing

    This section assumes the LCD bias power is controlled through GPIO1. The S1D13506 GPIO pins are multi-use pins and may not be available in all system designs. For further information on the availability of GPIO pins, see the S1D13506 Hardware Functional Specification, document number X25B-B-001-xx.
  • Page 273: Registers

    7.2.2 Enabling the LCD Panel If the LCD bias power supply timing requirements are different than those timings built into the S1D13506 automated LCD power sequencing, it may be necessary to manually enable the LCD panel. In such a case, the following procedure applies.
  • Page 274: Hardware Cursor/Ink Layer

    8 Hardware Cursor/Ink Layer 8.1 Introduction The S1D13506 supports either a Hardware Cursor or an Ink Layer for the LCD, and either a Hardware Cursor or an Ink Layer for the CRT/TV. The LCD and CRT/TV are supported independently, so it is possible to select combinations such as a Hardware Cursor on the LCD and an Ink Layer on the CRT/TV.
  • Page 275: Registers

    Epson Research and Development Page 41 Vancouver Design Center 8.2 Registers REG[070h] LCD Ink/Cursor Control Register Ink/Cursor Ink/Cursor Mode Bit 1 Mode Bit 0 REG[080h] CRT/TV Ink/Cursor Control Register CRT/TV CRT/TV Ink/Cursor Ink/Cursor Mode Bit 1 Mode Bit 0 The Ink/Cursor mode bits determine which of the Hardware Cursor or Ink Layer is active as shown in following table.
  • Page 276 Page 42 Epson Research and Development Vancouver Design Center REG[072h] LCD Cursor X Position Register 0 LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X...
  • Page 277 Epson Research and Development Page 43 Vancouver Design Center REG[074h] LCD Cursor Y Position Register 0 LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y...
  • Page 278 Page 44 Epson Research and Development Vancouver Design Center REG[076h] LCD Ink/Cursor Blue Color 0 Register Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Bit 4 Bit 3...
  • Page 279 Epson Research and Development Page 45 Vancouver Design Center REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0...