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Epson S1D13506 Technical Manual

S1d13506 color lcd/crt/tv controller.
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S1D13506 Color LCD/CRT/TV Controller
S1D13506
TECHNICAL MANUAL
Document Number: X25B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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   Summary of Contents for Epson S1D13506

  • Page 1

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 2

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...

  • Page 3: Riesstrasse, Millenia Tower Singapore

    Epson Research and Development Page 3 Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical manuals • Evaluation/Demonstration board manual Evaluation/Demonstration Board •...

  • Page 4

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...

  • Page 5

    S1D13506 COLOR LCD/CRT/TV CONTROLLER March 2001 The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.

  • Page 6

    Copyright ©1998, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document.

  • Page 7: Hardware Functional Specification

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 8

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 9: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........17 Scope .

  • Page 10: Table Of Contents

    Registers ........124 Initializing the S1D13506 ......124 8.1.1...

  • Page 11: Issue Date: 02/03/26 Page

    Epson Research and Development Page 5 Vancouver Design Center 8.3.2 General IO Pins Registers ....... 126 8.3.3...

  • Page 12: Table Of Contents

    15.4.3 Limitations ........208 16 EPSON Independent Simultaneous Display (EISD) ....209 16.1 Introduction .

  • Page 13

    Epson Research and Development Page 7 Vancouver Design Center 19.1 Display Modes ......221 19.2 Power Save Mode .

  • Page 14

    Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 15

    Epson Research and Development Page 9 Vancouver Design Center List of Tables Table 5-1: Host Bus Interface Pin Descriptions ......29 Table 5-2: Memory Interface Pin Descriptions .

  • Page 16

    Page 10 Epson Research and Development Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing..... . . 83 Table 7-23: Single Monochrome 8-Bit Panel A.C.

  • Page 17

    Table 10-1: S1D13506 Addressing ........181...

  • Page 18

    Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 19: Table Of Contents

    Figure 3-10: Typical System Diagram (Toshiba MIPS TX3912 Bus) ....26 Figure 4-1: S1D13506 Block Diagram ....... . . 27 Figure 5-1: Pinout Diagram .

  • Page 20: Table Of Contents

    Page 14 Epson Research and Development Vancouver Design Center Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing ..... . .85 Figure 7-26: Single Color 4-Bit Panel Timing .

  • Page 21

    Epson Research and Development Page 15 Vancouver Design Center Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL ..195 Figure 14-1: Ink/Cursor Data Format ....... . . 197 Figure 14-2: Unclipped Cursor Positioning .

  • Page 22

    Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 23: Introduction, Scope, Overview Description

    1.2 Overview Description The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.

  • Page 24: Features, Memory Interface, Cpu Interface

    • The complete 2M byte display buffer address space is directly and contiguously avail- able through the 21-bit address bus. 2.2 CPU Interface • Supports the following interfaces: • Epson E0C33 (16-bit interface to 32-bit microprocessor). • Hitachi SH-4 bus interface. • Hitachi SH-3 bus interface. • MIPS/ISA.

  • Page 25: Display Support, Display Modes, Display Features

    2.5 Display Features • SwivelView™: 90°, 180°, 270° hardware rotation of display image. • EPSON Independent Simultaneous Display (EISD): displays independent images on different displays (CRT or TV and passive or TFT/D-TFD panel). • Virtual Display Support: displays images larger than the panel size through the use of panning and scrolling.

  • Page 26: Clock Source, Acceleration, Mediaplug Interface, Miscellaneous

    Page 20 Epson Research and Development Vancouver Design Center 2.6 Clock Source • Memory clock can be derived from CLKI or BUSCLK pin. It can be internally divided by 2. • Pixel clock can be derived from CLKI, CLKI2, or BUSCLK pin. It can be internally divided by 2, 3 or 4.

  • Page 27: Typical System Implementation Diagrams, Figure 3-1: Typical System Diagram (generic Bus)

    Epson Research and Development Page 21 Vancouver Design Center 3 Typical System Implementation Diagrams For the pin mapping of each system implementation, see Table 5-7:, “CPU Interface Pin Mapping,” on page 40. Oscillator Oscillator Generic 4-bit FPDAT[7:4] L[3:0] Single FPSHIFT...

  • Page 28: Figure 3-2: Typical System Diagram (hitachi Sh-4 Bus)

    Page 22 Epson Research and Development Vancouver Design Center Oscillator Oscillator SH-4 4-bit FPDAT[7:4] D[3:0] A[21] M/R# Single FPSHIFT FPSHIFT CSn# A[20:1] AB[20:1] Display FPFRAME FPFRAME D[15:0] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# WE1# S1D13506 RD/WR# GPIOx RD/WR# RED,GREEN,BLUE...

  • Page 29: Figure 3-4: Typical System Diagram (mc68k Bus 1, Motorola 16-bit)

    Epson Research and Development Page 23 Vancouver Design Center Oscillator Oscillator MC68000 WE0# FPDAT[7:4] UD[3:0] 8-bit FPDAT[3:0] LD[3:0] A[23:21] M/R# Decoder Dual FC0, FC1 FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506...

  • Page 30: Figure 3-6: Typical System Diagram (motorola Powerpc Bus)

    Page 24 Epson Research and Development Vancouver Design Center Oscillator Oscillator PowerPC A[0:10] M/R# Decoder 16-bit FPDAT[15:0] D[15:0] Single Decoder FPSHIFT FPSHIFT A[11:31] AB[20:0] FPFRAME FPFRAME Display D[0:15] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# S1D13506 RD/WR# GPIOx RD/WR# TSIZ0...

  • Page 31: Figure 3-8: Typical System Diagram (pc Card Bus)

    Epson Research and Development Page 25 Vancouver Design Center Oscillator Oscillator PC Card FPDAT[15:8] UD[7:0] 16-bit FPDAT[7:0] LD[7:0] Decoder M/R# A[25:21] Dual FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506 WE0# CE2#...

  • Page 32: Figure 3-10: Typical System Diagram (toshiba Mips Tx3912 Bus)

    Page 26 Epson Research and Development Vancouver Design Center Oscillator Oscillator TX3912 M/R# FPDAT[11:0] D[11:0] 12-bit AB[16:13] FPSHIFT FPSHIFT A[12:0] AB[12:0] D[23:16] DB[15:8] FPFRAME FPFRAME Display D[31:24] DB[7:0] AB20 FPLINE FPLINE CARDREG* AB19 DRDY DRDY (MOD) S1D13506 CARDIORD* AB18 CARDIOWR*...

  • Page 33: Internal Description, Block Diagram Showing Pipelines

    Page 27 Vancouver Design Center 4 Internal Description 4.1 Block Diagram Showing Pipelines DRAM MediaPlug Camera Memory Controller Host Pipeline CRT/TV CRT/TV Pipeline Register Encoder Power Save Figure 4-1: S1D13506 Block Diagram Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 34: Pinout Diagram, Figure 5-1: Pinout Diagram

    Page 28 Epson Research and Development Vancouver Design Center 5 Pins 5.1 Pinout Diagram 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...

  • Page 35: Pin Description, Host Bus Interface

    Epson Research and Development Page 29 Vancouver Design Center 5.2 Pin Description Key: Input Output Bi-Directional (Input/Output) Analog Power pin CMOS level input CMOS level input with pull down resistor (typical values of 50Ω/90ΚΩ at 5V/3.3V respectively) CMOS level Schmitt input...

  • Page 36

    Page 30 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State • For Philips PR31500/31700 Bus, these pins are connected to V • For Toshiba TX3912 Bus, these pins are connected to V •...

  • Page 37

    • For all other busses, this input pin is used to select between the M/R# Hi-Z display buffer and register address spaces of the S1D13506. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping.

  • Page 38

    This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13506 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#).

  • Page 39

    Epson Research and Development Page 33 Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).

  • Page 40

    Page 34 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see “Summary of Configuration Options”.

  • Page 41: Memory Interface

    Epson Research and Development Page 35 Vancouver Design Center 5.2.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State • For dual-CAS# DRAM, this is the column address strobe for the lower byte (LCAS#).

  • Page 42

    Page 36 Epson Research and Development Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State 58, 60, 62, Multiplexed memory address - see Memory Interface Timing on page MA[8:0] 64, 66, 67, 70 for detailed functionality.

  • Page 43: Lcd Interface

    Epson Research and Development Page 37 Vancouver Design Center 5.2.3 LCD Interface Table 5-3: LCD Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State Panel data bus. Not all pins are used for some panels - see Table 5-9:, “LCD Interface Pin Mapping,”...

  • Page 44: Crt Interface, Miscellaneous

    Page 38 Epson Research and Development Vancouver Design Center 5.2.4 CRT Interface Table 5-4: CRT Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State HRTC Horizontal retrace signal for CRT VRTC Vertical retrace signal for CRT no output...

  • Page 45: Summary Of Configuration Options

    Epson Research and Development Page 39 Vancouver Design Center 5.3 Summary of Configuration Options Table 5-6: Summary of Power-On/Reset Options Pin Name value of this pin at rising edge of RESET# is used to configure:(1/0) Not used, value of this pin at rising edge of RESET# can be read at REG[00Ch] bit 0...

  • Page 46: Multiple Function Pin Mapping

    Note AB0 is not used internally for these busses and must be connected to either V For further information on interfacing the S1D13506 to the PC Card bus, see Interfac- ing to the PC Card Bus, document number X25B-G-005-xx. S1D13506...

  • Page 47

    Epson Research and Development Page 41 Vancouver Design Center Table 5-8: Memory Interface Pin Mapping FPM/EDO-DRAM S1D13506 Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 Pin Names 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# MD[15:0] D[15:0] MA[8:0] A[8:0] GPIO3...

  • Page 48

    Page 42 Epson Research and Development Vancouver Design Center Table 5-9: LCD Interface Pin Mapping Monochrome Passive Color Passive Panel Panel S1D13506 Color TFT/D-TFD Panel Single Single Single Dual Single Single Dual Names Format 1 Format 2 4-bit 8-bit 8-bit...

  • Page 49

    Epson Research and Development Page 43 Vancouver Design Center Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping MD14, MD7, MD6 MA11 MA10 DRDY GPIO2 GPIO1 GPIO3 DRDY GPIO2 GPIO1 DRDY GPIO2 GPIO1 DRDY MA11 MA10 DRDY VMPEPWR GPIO1 GPIO3...

  • Page 50: Crt/tv Interface, Figure 5-2: External Circuitry For Crt/tv Interface

    Page 44 Epson Research and Development Vancouver Design Center 5.5 CRT/TV Interface The following figure shows external circuitry for the CRT/TV interface. CRT/TV CRT Only CRT Only (REG[05Bh] bit 3 = 0) (REG[05Bh] bit 3 =1) (REG[05Bh] bit 3 =1) DAC V = 3.3V...

  • Page 51: D.c. Characteristics

    Epson Research and Development Page 45 Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Supply Voltage - 0.3 to 6.0 DAC V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to V + 0.5...

  • Page 52

    Page 46 Epson Research and Development Vancouver Design Center Table 6-4: Electrical Characteristics for VDD = 3.3V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -2mA (Type1), High Level Output Voltage - 0.3...

  • Page 53

    Epson Research and Development Page 47 Vancouver Design Center Table 6-5: Electrical Characteristics for VDD = 3.0V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -1.8mA (Type1), High Level Output Voltage - 0.3...

  • Page 54: A.c. Characteristics, Cpu Interface Timing, Generic Timing

    Page 48 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: = 3.0V ± 10% and V = 5.0V ± 10% = -40° C to 85° C and T for all inputs must be < 5 ns (10% ~ 90%)

  • Page 55

    Epson Research and Development Page 49 Vancouver Design Center Table 7-1: Generic Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,...

  • Page 56: Hitachi Sh-4 Interface Timing

    (BUSCLK input is not divided). Note The SH-4 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. The SH-4 read-to-write idle cycle transition must be set to a non-zero value (with reference to BUSCLK).

  • Page 57

    Epson Research and Development Page 51 Vancouver Design Center Table 7-2: Hitachi SH-4 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...

  • Page 58: Hitachi Sh-3 Interface Timing

    BUSCLK cannot be divided by 2 in SH-3 interface mode. MD12 must be set to 0 (BUSCLK input is not divided). Note The SH-3 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. S1D13506...

  • Page 59

    Epson Research and Development Page 53 Vancouver Design Center Table 7-3: Hitachi SH-3 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...

  • Page 60: Mips/isa Interface Timing (e.g. Nec Vr41xx), Mips/isa Interface Timing (e.g. Nec Vr41xx)

    Page 54 Epson Research and Development Vancouver Design Center 7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) BUSCLK BUSCLK LatchA20 SA[19:0] M/R#, SBHE# MEMR# MEMW# IOCHRDY SD[15:0](write) SD[15:0](read) Figure 7-4: MIPS/ISA Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).

  • Page 61

    Epson Research and Development Page 55 Vancouver Design Center Table 7-4: MIPS/ISA Timing 3.0V 5.0V Symbol Parameter Units Clock frequency BUSCLK Clock period BUSCLK BUSCLK BUSCLK Clock pulse width high Clock pulse width low LatchA20, SA[19:0], M/R#, SBHE# setup to first...

  • Page 62: Motorola Mc68k Bus 1 Interface Timing (e.g. Mc68000)

    Page 56 Epson Research and Development Vancouver Design Center 7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) A[20:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) Figure 7-5: Motorola MC68000 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).

  • Page 63

    Epson Research and Development Page 57 Vancouver Design Center Table 7-5: Motorola MC68000 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and...

  • Page 64: Motorola Mc68k Bus 2 Interface Timing (e.g. Mc68030)

    Page 58 Epson Research and Development Vancouver Design Center 7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) A[20:0] SIZ[1:0] M/R# R/W# DSACK1# D[31:16](write) D[31:16](read) Figure 7-6: Motorola MC68030 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).

  • Page 65

    Epson Research and Development Page 59 Vancouver Design Center Table 7-6: Motorola MC68030 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0,...

  • Page 66: Motorola Powerpc Interface Timing (e.g. Mpc8xx, Mc68040, Coldfire)

    Page 60 Epson Research and Development Vancouver Design Center 7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) CLKOUT CLKOUT A[11:31], RD/WR# TSIZ[0:1], M/R# t15 t16 D[0:15](write) D[0:15](read) Figure 7-7: Motorola PowerPC Timing Note BUSCLK cannot be divided by 2 in PowerPC interface mode. MD12 must be set to 0 (BUSCLK input is not divided).

  • Page 67

    Epson Research and Development Page 61 Vancouver Design Center Table 7-7: Motorola PowerPC Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CLKOUT Clock period CLKOUT CLKOUT CLKOUT Clock pulse width low Clock pulse width high AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup...

  • Page 68: Pc Card Timing (e.g. Strongarm), Pc Card Timing (e.g. Strongarm)

    Page 62 Epson Research and Development Vancouver Design Center 7.1.8 PC Card Timing (e.g. StrongARM) (provided externally) A[20:1] M/R# CE1#, CE2# WAIT# D[15:0](write) D[15:0](read) Figure 7-8: PC Card Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).

  • Page 69

    Epson Research and Development Page 63 Vancouver Design Center Table 7-8: PC Card Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either...

  • Page 70: Philips Interface Timing (e.g. Pr31500/pr31700), Philips Interface Timing (e.g. Pr31500/pr)

    Page 64 Epson Research and Development Vancouver Design Center 7.1.9 Philips Interface Timing (e.g. PR31500/PR31700) DCLKOUT DCLKOUT ADDR[12:0] /CARDREG /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD /CARDxWAIT D[31:16](write) D[31:16](read) Figure 7-9: Philips Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 71

    Epson Research and Development Page 65 Vancouver Design Center Table 7-9: Philips Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...

  • Page 72: Toshiba Interface Timing (e.g. Tx39xx), Toshiba Interface Timing (e.g. Tx39xx)

    Page 66 Epson Research and Development Vancouver Design Center 7.1.10 Toshiba Interface Timing (e.g. TX39xx) DCLKOUT DCLKOUT ADDR[12:0] CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) Figure 7-10: Toshiba Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 73

    Epson Research and Development Page 67 Vancouver Design Center Table 7-10: Toshiba Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...

  • Page 74: Clock Timing, Input Clocks

    Page 68 Epson Research and Development Vancouver Design Center 7.2 Clock Timing 7.2.1 Input Clocks V IL Figure 7-11: CLKI Clock Input Requirements Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally Symbol Parameter Units Input Clock Frequency Input Clock Period...

  • Page 75: Internal Clocks

    Epson Research and Development Page 69 Vancouver Design Center 7.2.2 Internal Clocks Table 7-13: Internal Clock Requirements Symbol Parameter Units Memory Clock Frequency MCLK LCD Pixel Clock Frequency LCD PCLK CRT/TV Pixel Clock Frequency Note 1 CRT/TV PCLK MediaPlug Clock Frequency MediaPlug Clock 1.

  • Page 76: Memory Interface Timing, Edo-dram Read, Write, Read-write Timing

    Page 70 Epson Research and Development Vancouver Design Center 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE# (read) MD (read) WE#(write) t20 t21 MD(write) Figure 7-12: EDO-DRAM Page Mode Timing...

  • Page 77

    Epson Research and Development Page 71 Vancouver Design Center Table 7-14: EDO-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)

  • Page 78: Edo-dram Cas Before Ras Refresh Timing

    Page 72 Epson Research and Development Vancouver Design Center 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-14: EDO-DRAM CAS Before RAS Refresh Timing Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock period...

  • Page 79: Edo-dram Self-refresh Timing

    Epson Research and Development Page 73 Vancouver Design Center 7.3.3 EDO-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-15: EDO - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.

  • Page 80: Fpm-dram Read, Write, Read-write Timing

    Page 74 Epson Research and Development Vancouver Design Center 7.3.4 FPM-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE#(read) MD(read) WE#(write) t18 t19 MD(write) Figure 7-16: FPM-DRAM Page Mode Timing Memory Clock RAS# CAS# t10 t11...

  • Page 81

    Epson Research and Development Page 75 Vancouver Design Center Table 7-17: FPM-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)

  • Page 82: Fpm-dram Cas Before Ras Refresh Timing

    Page 76 Epson Research and Development Vancouver Design Center 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-18: FPM-DRAM CAS Before RAS Refresh Timing Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock RAS# precharge time (REG[02Ah] bits 1-0 = 00) 2.45 t1...

  • Page 83: Fpm-dram Self-refresh Timing

    Epson Research and Development Page 77 Vancouver Design Center 7.3.6 FPM-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-19: FPM - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.

  • Page 84: Power Sequencing, Lcd Power Sequencing

    Page 78 Epson Research and Development Vancouver Design Center 7.4 Power Sequencing 7.4.1 LCD Power Sequencing #RESET LCD Enable Bit (REG[1FCh] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Figure 7-20: LCD Panel Power-off/Power-on Timing...

  • Page 85: Power Save Mode

    Epson Research and Development Page 79 Vancouver Design Center 7.4.2 Power Save Mode Power Save Mode Enable Bit (REG[1F0h] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Memory Controller Power Save Status Bit...

  • Page 86

    Page 80 Epson Research and Development Vancouver Design Center Table 7-21: Power Save Mode Timing Symbol Parameter Units FPFRAME Power Save Mode Enable Bit high to FPFRAME inactive FPLINE Power Save Mode Enable Bit low to FPFRAME active FPLINE Power Save Mode Enable Bit high to FPLINE, FPSHIFT, FPDATA,...

  • Page 87: Display Interface, Single Monochrome 4-bit Panel Timing, Figure 7-22: Single Monochrome 4-bit Panel Timing

    Epson Research and Development Page 81 Vancouver Design Center 7.5 Display Interface 7.5.1 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPDAT[7:4] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-317 1-318...

  • Page 88: Figure 7-23: Single Monochrome 4-bit Panel A.c. Timing

    Page 82 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-23: Single Monochrome 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 89

    Epson Research and Development Page 83 Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 90: Single Monochrome 8-bit Panel Timing, Figure 7-24: Single Monochrome 8-bit Panel Timing

    Page 84 Epson Research and Development Vancouver Design Center 7.5.2 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-633 FPDAT6 1-10 1-634 FPDAT5...

  • Page 91: Figure 7-25: Single Monochrome 8-bit Panel A.c. Timing

    Epson Research and Development Page 85 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 92

    Page 86 Epson Research and Development Vancouver Design Center Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 93: Single Color 4-bit Panel Timing, Figure 7-26: Single Color 4-bit Panel Timing

    Epson Research and Development Page 87 Vancouver Design Center 7.5.3 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 FPDAT[7:4] LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-G2 1-B3 1-B319 FPDAT7 1-R320...

  • Page 94: Figure 7-27: Single Color 4-bit Panel A.c. Timing

    Page 88 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-27: Single Color 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 95

    Epson Research and Development Page 89 Vancouver Design Center Table 7-24: Single Color 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 96: Single Color 8-bit Panel Timing (format 1)

    Page 90 Epson Research and Development Vancouver Design Center 7.5.4 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT FPSHIFT2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12...

  • Page 97: Figure 7-29: Single Color 8-bit Panel A.c. Timing (format)

    Epson Research and Development Page 91 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 FPDAT[7:0] Figure 7-29: Single Color 8-Bit Panel A.C. Timing (Format 1) Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 98

    Page 92 Epson Research and Development Vancouver Design Center Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 99: Single Color 8-bit Panel Timing (format 2), Figure 7-30: Single Color 8-bit Panel Timing (format)

    Epson Research and Development Page 93 Vancouver Design Center 7.5.5 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-B3 1-G6 1-G638...

  • Page 100: Figure 7-31: Single Color 8-bit Panel A.c. Timing (format)

    Page 94 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 2) S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 101

    Epson Research and Development Page 95 Vancouver Design Center Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 102: Single Color 16-bit Panel Timing, Figure 7-32: Single Color 16-bit Panel Timing

    Page 96 Epson Research and Development Vancouver Design Center 7.5.6 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE FPDAT[15:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE HNDP FPSHIFT Invalid 1-G6 1-B11 1-G635 1-R1 Invalid FPDAT15 Invalid...

  • Page 103: Figure 7-33: Single Color 16-bit Panel A.c. Timing

    Epson Research and Development Page 97 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 7-33: Single Color 16-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 104

    Page 98 Epson Research and Development Vancouver Design Center Table 7-27: Single Color 16-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 105: Single Color 16-bit Panel Timing With External Circuit

    Epson Research and Development Page 99 Vancouver Design Center 7.5.7 Single Color 16-Bit Panel Timing with External Circuit VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2...

  • Page 106: Figure 7-36: Single Color 16-bit Panel (with External Circuit) A.c. Timing

    Page 100 Epson Research and Development Vancouver Design Center D[7:0] TO 16-BIT PANEL FPDAT[7:0] D[15:8] FROM S1D13506 FPSHIFT Figure 7-35: External Circuit for Color Single 16-Bit Panel When the Media Plug is Enabled Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing...

  • Page 107

    Epson Research and Development Page 101 Vancouver Design Center Table 7-28: Single Color 16-Bit Panel (with External Circuit) A.C. Timing Min. Max. Symbol Parameter Nominal Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1)

  • Page 108: Dual Monochrome 8-bit Panel Timing, Figure 7-37: Dual Monochrome 8-bit Panel Timing

    Page 102 Epson Research and Development Vancouver Design Center 7.5.8 Dual Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)

  • Page 109: Figure 7-38: Dual Monochrome 8-bit Panel A.c. Timing

    Epson Research and Development Page 103 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-38: Dual Monochrome 8-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 110

    Page 104 Epson Research and Development Vancouver Design Center Table 7-29: Dual Monochrome 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 111: Dual Color 8-bit Panel Timing, Figure 7-39: Dual Color 8-bit Panel Timing

    Epson Research and Development Page 105 Vancouver Design Center 7.5.9 Dual Color 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)

  • Page 112: Figure 7-40: Dual Color 8-bit Panel A.c. Timing

    Page 106 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-40: Dual Color 8-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 113

    Epson Research and Development Page 107 Vancouver Design Center Table 7-30: Dual Color 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 114: Dual Color 16-bit Panel Timing, Figure 7-41: Dual Color 16-bit Panel Timing

    Page 108 Epson Research and Development Vancouver Design Center 7.5.10 Dual Color 16-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE DRDY (MOD)

  • Page 115: Figure 7-42: Dual Color 16-bit Panel A.c. Timing

    Epson Research and Development Page 109 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 7-42: Dual Color 16-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 116

    Page 110 Epson Research and Development Vancouver Design Center Table 7-31: Dual Color 16-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...

  • Page 117: Dual Color 16-bit Panel Timing With External Circuit

    Epson Research and Development Page 111 Vancouver Design Center 7.5.11 Dual Color 16-Bit Panel Timing with External Circuit VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242...

  • Page 118: Figure 7-45: Dual Color 16-bit Panel (with External Circuit) A.c. Timing

    Page 112 Epson Research and Development Vancouver Design Center UD[3:0] LD[3:0] TO 16-BIT PANEL FPDAT[7:4] UD[7:4] FPDAT[3:0] LD[7:4] FROM S1D13506 FPSHIFT Figure 7-44: External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled Sync Timing FPFRAME FPLINE...

  • Page 119

    Epson Research and Development Page 113 Vancouver Design Center Table 7-32: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1)

  • Page 120: Tft/d-tfd Panel Timing, Figure 7-46: Tft/d-tfd Panel Timing

    Page 114 Epson Research and Development Vancouver Design Center 7.5.12 TFT/D-TFD Panel Timing VNDP FPFRAME FPLINE LINE480 LINE1 LINE480 R[5:1], G[5:0], B[5:1] DRDY FPLINE HNDP HNDP FPSHIFT DRDY R[5:1] 1-640 G [5:0] 1-640 B[5:1] 1-640 Note: DRDY is used to indicate the first pixel...

  • Page 121: Figure 7-47: Tft/d-tfd A.c. Timing

    Epson Research and Development Page 115 Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Figure 7-47: TFT/D-TFD A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...

  • Page 122

    Page 116 Epson Research and Development Vancouver Design Center Table 7-33: TFT/D-TFD A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPSHIFT period Ts (note 1) FPSHIFT pulse width high FPSHIFT pulse width low data setup to FPSHIFT falling edge...

  • Page 123: Crt Timing, Figure 7-48: Crt Timing

    Epson Research and Development Page 117 Vancouver Design Center 7.5.13 CRT Timing VNDP VRTC HRTC LINE480 LINE1 LINE480 RED,GREEN,BLUE HRTC HNDP HNDP 1-640 RED,GREEN,BLUE Example Timing for 640x480 CRT Figure 7-48: CRT Timing = Vertical Display Period = (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1...

  • Page 124

    Page 118 Epson Research and Development Vancouver Design Center VRTC HRTC Figure 7-49: CRT A.C. Timing Table 7-34: CRT A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting VRTC cycle time note 1 1152 lines VRTC pulse width low...

  • Page 125: Tv Timing, Tv Output Timing

    Epson Research and Development Page 119 Vancouver Design Center 7.6 TV Timing 7.6.1 TV Output Timing The overall NTSC and PAL video timing is shown in Figure 7-50: and Figure 7-51: respec- tively. Register Programming: vertical blanking interval = 20 lines...

  • Page 126: Figure 7-51: Pal Video Timing

    Page 120 Epson Research and Development Vancouver Design Center Register Programming: vertical blanking interval = 25 lines Vertical Non-Display Period = 26 VRTC Start Position = 0 623 624 625 pre-equalizing vertical sync post-equalizing Field 1 pulse interval pulse interval...

  • Page 127

    Epson Research and Development Page 121 Vancouver Design Center Active Line Blanking 40 IRE Level Blanking Level Equalizing Pulse Vertical Sync Pulse Start of Horizontal Sync Figure 7-52: Horizontal Timing for NTSC/PAL Table 7-35: Horizontal Timing for NTSC/PAL Symbol Parameter...

  • Page 128: Figure 7-53: Vertical Timing For Ntsc/pal

    Page 122 Epson Research and Development Vancouver Design Center 909 (NTSC) 1134 (PAL) Vertical Vertical Non-Display Sync Period Field Vertical Odd Lines (1, 3, 5, ...) Display Period Vertical Non-Display Vertical Period Sync Even Field Vertical Even Lines (2, 4, 6, ...)

  • Page 129: Mediaplug Interface Timing

    Epson Research and Development Page 123 Vancouver Design Center 7.7 MediaPlug Interface Timing VMPCLK VMPCLKN VMPDIN[3:0] VMPCTRL VMPLCTRL VMPDout Figure 7-54: MediaPlug A.C. Timing Note The above timing diagram assumes no load. Table 7-37: MediaPlug A.C. Timing Symbol Parameter Units...

  • Page 130: Registers, Register/memory Select Bit, Register Mapping, Initializing The S1d

    Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13506 registers. It also provides detailed information about the layout and usage of each register. 8.1 Initializing the S1D13506 Before programming the S1D13506 registers, the Register/Memory Select bit (REG[000h] bit 7) must be set.

  • Page 131: Register Descriptions, Basic Registers

    7-2 Product Code Bits [5:0] This is a read-only register that indicates the product code of the chip. The product code for S1D13506 is 000100b. bits 1-0 Revision Code Bits [1:0] This is a read-only register that indicates the revision code of the chip. The revision code is 01b.

  • Page 132: General Io Pins Registers

    Page 126 Epson Research and Development Vancouver Design Center 8.3.2 General IO Pins Registers General IO Pins Configuration Register REG[004h] GPIO3 Pin GPIO2 Pin GPIO1 Pin Reserved Reserved Reserved Reserved Reserved IO Config. IO Config. IO Config. bit 3 GPIO3 Pin IO Configuration When this bit = 1, GPIO3 is configured as an output pin.

  • Page 133

    Epson Research and Development Page 127 Vancouver Design Center General IO Pins Control Register REG[008h] GPIO3 Pin GPIO2 Pin GPIO1 Pin Reserved Reserved Reserved Reserved Reserved IO Status IO Status IO Status bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low.

  • Page 134: Md Configuration Readback Registers, Clock Configuration Registers

    Page 128 Epson Research and Development Vancouver Design Center 8.3.3 MD Configuration Readback Registers MD Configuration Status Register 0 REG[00Ch] MD[7] MD[6] MD[5] MD[4] MD[3] MD[2] MD[1] MD[0] Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config.

  • Page 135

    Epson Research and Development Page 129 Vancouver Design Center LCD Pixel Clock Configuration Register REG[014h] LCD PCLK LCD PCLK LCD PCLK LCD PCLK Divide Select Divide Select Source Select Source Select Bit 1 Bit 0 Bit 1 Bit 0 bits 5-4...

  • Page 136

    Page 130 Epson Research and Development Vancouver Design Center bits 5-4 CRT/TV PCLK Divide Select Bits[1:0] These bits determine the divide used to generate the CRT/TV pixel clock from the CRT/TV pixel clock source. Table 8-6: CRT/TV PCLK Divide Selection...

  • Page 137

    Epson Research and Development Page 131 Vancouver Design Center bits 1-0 MediaPlug Clock Source Select Bits [1:0] These bits determine the source of the MediaPlug Clock for the MediaPlug Interface. See Section 7.7, “MediaPlug Interface Timing” on page 123 for AC Timing.

  • Page 138: Memory Configuration Registers

    Page 132 Epson Research and Development Vancouver Design Center 8.3.5 Memory Configuration Registers Memory Configuration Register REG[020h] Memory Type Memory Type Bit 1 Bit 0 bits 1-0 Memory Type Bits [1:0] These bits specify the memory type. Table 8-11: Memory Type Selection...

  • Page 139

    Epson Research and Development Page 133 Vancouver Design Center bits 2-0 DRAM Refresh Rate Select Bits [2:0] These bits specify the divide used to generate the DRAM refresh clock rate, which is equal (ValueOfTheseBits + 6) to 2 , from the MCLK source (either BUSCLK or CLKI as determined by REG[010h] bit 0).

  • Page 140

    Page 134 Epson Research and Development Vancouver Design Center DRAM Timing Control Register 0 REG[02Ah] DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing Control Control Control Control Control Control Control Control Register...

  • Page 141: Panel Configuration Registers

    When this bit = 1, the EL Panel support circuit is enabled. When this bit = 0, there is no hardware effect. This bit enables the S1D13506 built-in circuit for EL panels which require the Frame Rate Modulation (FRM) to remain static for one frame after every 262143 frames (approxi- mately 1 hour at 60Hz refresh).

  • Page 142

    Page 136 Epson Research and Development Vancouver Design Center MOD Rate Register REG[031h] MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit bits 5-0 MOD Rate Bits [5:0] For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal (DRDY).

  • Page 143

    Epson Research and Development Page 137 Vancouver Design Center LCD Horizontal Non-Display Period Register REG[034h] Horizontal Horizontal Horizontal Horizontal Horizontal Non-Display Non-Display Non-Display Non-Display Non-Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0...

  • Page 144

    Page 138 Epson Research and Development Vancouver Design Center TFT FPLINE Pulse Width Register REG[036h] LCD FPLINE TFT FPLINE TFT FPLINE TFT FPLINE TFT FPLINE Polarity Pulse Width Pulse Width Pulse Width Pulse Width Select Bit 3 Bit 2 Bit 1...

  • Page 145

    Epson Research and Development Page 139 Vancouver Design Center LCD Vertical Non-Display Period Register REG[03Ah] LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Period Status Period Bit 5...

  • Page 146: Lcd Display Mode Registers

    Page 140 Epson Research and Development Vancouver Design Center TFT FPFRAME Pulse Width Register REG[03Ch] FPFRAME FPFRAME FPFRAME FPFRAME Polarity Pulse Width Pulse Width Pulse Width Select Bit 2 Bit 1 Bit 0 bit 7 LCD FPFRAME Polarity Select This bit selects the polarity of FPFRAME for all LCD panels.

  • Page 147

    Epson Research and Development Page 141 Vancouver Design Center bit 4 SwivelView™ Enable Bit 1 When this bit = 1, the LCD display image is rotated 180° clockwise. Please refer to Section 15, “SwivelView™” on page 200 for application and limitations.

  • Page 148

    RGB component which results in 256K colors per pixel (64x64x64). For the S1D13506, 16 bpp is arranged as 5-6-5 RGB. In this mode, when dithering is enabled, the LUT is bypassed and the original 16-bit data is used as a pointer into the 64 shades per color in the following manner.

  • Page 149

    Epson Research and Development Page 143 Vancouver Design Center LCD Display Start Address Register 0 REG[042h] LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display Start Address Start Address Start Address Start Address...

  • Page 150

    Page 144 Epson Research and Development Vancouver Design Center LCD Pixel Panning Register REG[048h] LCD Pixel LCD Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 bits 3-2 Reserved. Must be set to 0. bits 1-0 LCD Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the LCD display.

  • Page 151: Crt/tv Configuration Registers

    Epson Research and Development Page 145 Vancouver Design Center LCD Display FIFO Low Threshold Control Register REG[04Bh] LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display FIFO Low FIFO Low FIFO Low FIFO Low FIFO Low FIFO Low...

  • Page 152

    Page 146 Epson Research and Development Vancouver Design Center CRT/TV HRTC Start Position Register REG[053h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV HRTC Start HRTC Start HRTC Start HRTC Start HRTC Start HRTC Start Position Bit 5 Position Bit 4 Position Bit 3...

  • Page 153

    Epson Research and Development Page 147 Vancouver Design Center CRT/TV Vertical Display Height Register 0 REG[056h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display...

  • Page 154

    Page 148 Epson Research and Development Vancouver Design Center CRT/TV VRTC Start Position Register REG[059h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start VRTC Start Position Bit 6 Position Bit 5...

  • Page 155

    Epson Research and Development Page 149 Vancouver Design Center CRT/TV Output Control Register REG[05Bh] TV S-Video/ DAC Output Chrominance Luminance Composite PAL/NTSC Level Select Filter Enable Filter Enable Output Select Output Select bit 5 TV Chrominance Filter Enable When this bit = 1, the TV chrominance filter is enabled.

  • Page 156: Crt/tv Display Mode Registers

    Page 150 Epson Research and Development Vancouver Design Center 8.3.9 CRT/TV Display Mode Registers CRT/TV Display Mode Register REG[060h] CRT/TV Bit- CRT/TV Bit- CRT/TV Bit- CRT/TV per-pixel per-pixel per-pixel Display Blank Select Bit 2 Select Bit 1 Select Bit 0...

  • Page 157

    Epson Research and Development Page 151 Vancouver Design Center CRT/TV Display Start Address Register 0 REG[062h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Display Start Display Start Display Start Display Start Display Start Display Start Display Start Display Start...

  • Page 158

    Page 152 Epson Research and Development Vancouver Design Center CRT/TV Pixel Panning Register REG[068h] CRT/TV Pixel CRT/TV Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 bits 3-2 Reserved. Must be set to 0. bits 1-0 CRT/TV Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the CRT/TV display.

  • Page 159: Lcd Ink/cursor Registers

    Epson Research and Development Page 153 Vancouver Design Center CRT/TV Display FIFO Low Threshold Control Register REG[06Bh] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Threshold Threshold Threshold Threshold Threshold...

  • Page 160

    Page 154 Epson Research and Development Vancouver Design Center LCD Ink/Cursor Start Address Register REG[071h] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7...

  • Page 161

    Epson Research and Development Page 155 Vancouver Design Center LCD Cursor Y Position Register 0 REG[074h] LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y...

  • Page 162

    Page 156 Epson Research and Development Vancouver Design Center LCD Ink/Cursor Red Color 0 Register REG[078h] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Red Color 0 Red Color 0 Red Color 0 Red Color 0 Red Color 0 Bit 4 Bit 3...

  • Page 163: Crt/tv Ink/cursor Registers

    Epson Research and Development Page 157 Vancouver Design Center LCD Ink/Cursor FIFO High Threshold Register REG[07Eh] Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor FIFO High FIFO High FIFO High FIFO High Threshold Threshold Threshold Threshold Bit 3 Bit 2 Bit 1 Bit 0...

  • Page 164

    Page 158 Epson Research and Development Vancouver Design Center CRT/TV Ink/Cursor Start Address Register REG[081h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address...

  • Page 165

    Epson Research and Development Page 159 Vancouver Design Center REG[082h] bits 7-0 CRT/TV Cursor X Position Bits [9:0] REG[083h] bits 1-0 A 10-bit register that defines the horizontal position of the CRT/TV Cursor’s top left hand corner in pixel units. This register is only valid when Cursor has been selected in the CRT/TV Ink/Cursor select registers.

  • Page 166

    Page 160 Epson Research and Development Vancouver Design Center CRT/TV Ink/Cursor Green Color 0 Register REG[087h] CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 0 Green Color 0 Green Color 0 Green Color 0...

  • Page 167: Bitblt Configuration Registers

    Epson Research and Development Page 161 Vancouver Design Center CRT/TV Ink/Cursor FIFO High Threshold Register REG[08Eh] CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor FIFO High FIFO High FIFO High FIFO High Threshold Threshold Threshold Threshold Bit 3 Bit 2...

  • Page 168

    Page 162 Epson Research and Development Vancouver Design Center bit 6 BitBLT FIFO Not-Empty Status This is a read-only status bit. When this bit = 1, the BitBLT FiFO has at least one data. When this bit = 0, the BitBLT FIFO is empty.

  • Page 169

    Epson Research and Development Page 163 Vancouver Design Center BitBLT Control Register 1 REG[101h] BitBLT Color Reserved Format Select bit 4 Reserved. Must be set to 0. bit 0 BitBLT Color Format Select This bit selects the color format that the 2D operation is applied to.

  • Page 170

    Page 164 Epson Research and Development Vancouver Design Center BitBLT Operation Register REG[103h] BitBLT BitBLT BitBLT BitBLT Operation Operation Operation Operation Bit 3 Bit 2 Bit 1 Bit 0 bits 3-0 BitBLT Operation Bits [3:0] Specifies the 2D Operation to be carried out based on the following table:...

  • Page 171

    Epson Research and Development Page 165 Vancouver Design Center BitBLT Source Start Address Register 0 REG[104h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Source Start Source Start Source Start Source Start Source Start Source Start Source Start Source Start...

  • Page 172

    Page 166 Epson Research and Development Vancouver Design Center BitBLT Destination Start Address Register 0 REG[108h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Destination Destination Destination Destination Destination Destination Destination Destination Start Address Start Address Start Address Start Address...

  • Page 173

    Epson Research and Development Page 167 Vancouver Design Center BitBLT Width Register 0 REG[110h] BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width BitBLT Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...

  • Page 174

    Page 168 Epson Research and Development Vancouver Design Center BitBLT Background Color Register 0 REG[114h] BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Background Background Background Background Background Background Background Background Color Color Color Color Color Color Color Color Bit 7...

  • Page 175: Look-up Table Registers

    7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13506 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 12, “Look-Up Table Architecture” on page 185 for details.

  • Page 176: Power Save Configuration Registers

    Page 170 Epson Research and Development Vancouver Design Center Look-Up Table Data Register REG[1E4h] LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit 0 bits 7-4 LUT Data Bits [3:0] This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the pointer controlled by the Look-Up Table Address Register (REG[1E2h]).

  • Page 177: Miscellaneous Registers

    Epson Research and Development Page 171 Vancouver Design Center bit 0 Memory Controller Power Save Status This bit indicates the power save state of the memory controller. When this bit = 1, the memory controller is powered down and is either in self refresh or no refresh mode.

  • Page 178: Common Display Mode Register

    Page 172 Epson Research and Development Vancouver Design Center 8.3.16 Common Display Mode Register Display Mode Register REG[1FCh] SwivelView™ Display Mode Display Mode Display Mode Enable Bit 0 Select Bit 2 Select Bit 1 Select Bit 0 bit 6 SwivelView™ Enable Bit 0 When this bit = 1, the LCD and CRT display image is rotated 90°...

  • Page 179: Mediaplug Register Descriptions

    Vancouver Design Center 8.3.17 MediaPlug Register Descriptions The S1D13506 has built-in support for Winnov’s MediaPlug connection designed for video cameras. The following registers are used to control the connection and accept data from the camera. The MediaPlug registers decode A11-A0 and require A20 = 0 and A12 = 1. The MediaPlug registers are 16-bit wide.

  • Page 180

    Page 174 Epson Research and Development Vancouver Design Center bit 7 Cable Detected Status (MediaPlug Parameter Rstat) The cable detected status as determined by the MPD(1) pin. When this bit = 0, a MediaPlug cable is connected. When this bit = 1, a MediaPlug cable is not detected.

  • Page 181

    Epson Research and Development Page 175 Vancouver Design Center MediaPlug Reserved LCMD Register REG[1002h] LCMD Bit 23 LCMD Bit 22 LCMD Bit 21 LCMD Bit 20 LCMD Bit 19 LCMD Bit 18 LCMD Bit 17 LCMD Bit 16 LCMD Bit 31...

  • Page 182

    Page 176 Epson Research and Development Vancouver Design Center bit 2-0 Command Field (MediaPlug Parameter C) Selects the command as follows: Table 8-41: MediaPlug Commands Command Field Command [bits 2:0] Remote-Reset: Hardware reset of remote. Stream-End: Indicates end of data streaming operation.

  • Page 183: Bitblt Data Registers Descriptions

    Epson Research and Development Page 177 Vancouver Design Center 8.3.18 BitBLT Data Registers Descriptions The BitBLT data registers decode A19-A0 and require A20 = 1. The BitBLT data registers are 16-bit wide. Byte access to the BitBLT data registers is not allowed.

  • Page 184: D Bitblt Engine, Functional Description, Bitblt Operations

    Epson Research and Development Vancouver Design Center 9 2D BitBLT Engine The S1D13506 has a built-in 2D BitBLT engine which increases the performance of Bit Block Transfers (BitBLT). This section will discuss the BitBLT engine design and functionality. 9.1 Functional Description The 2D BitBLT engine is designed using a 16-bit architecture.

  • Page 185

    Epson Research and Development Page 179 Vancouver Design Center Pattern Fill The Pattern Fill BitBLT fills a specified BitBLT area with an 8 pixel by 8 line pattern in full color defined in off-screen display buffer. The pattern data has to be stored in a contiguous address (i.e.

  • Page 186

    Page 180 Epson Research and Development Vancouver Design Center Transparent Move BitBLT The Transparent Move BitBLT supports bit block transfers from display buffer to display buffer in positive direction only. When the source color is equal to key color, which is defined in Background Color Register, the destination area is not updated.

  • Page 187: Display Buffer

    The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below: Table 10-1: S1D13506 Addressing M/R# Access Register access - see Section 8.2, “Register Mapping”...

  • Page 188: Image Buffer, Ink Layer/hardware Cursor Buffers, Dual Panel Buffer

    Page 182 Epson Research and Development Vancouver Design Center 10.1 Image Buffer The image buffer contains the formatted display mode data – see Section 11.1, “Display Mode Data Format” on page 183. The displayed image(s) may occupy only a portion of this space; the remaining area may be used for multiple images –...

  • Page 189: Display Configuration, Display Mode Data Format, Figure 11-1: 4/8/15/16 Bit-per-pixel Format Memory Organization

    Epson Research and Development Page 183 Vancouver Design Center 11 Display Configuration 11.1 Display Mode Data Format The following diagrams show the display mode data formats for a little endian system: 4 bpp: bit 7 bit 0 Byte 0 Byte 1...

  • Page 190: Image Manipulation

    LCD display. The screen image on the CRT/TV is manipulated similarly. When EISD is enabled (see Section 16, “EPSON Independent Simultaneous Display (EISD)” on page 209), the images on the LCD and on the CRT/TV are independent of each other.

  • Page 191: Look-up Table Architecture, Monochrome Modes

    Epson Research and Development Page 185 Vancouver Design Center 12 Look-Up Table Architecture The following depictions are intended to show the display data output path only. 12.1 Monochrome Modes The green LUT is used for all monochrome modes. 4 Bit-Per-Pixel Monochrome Mode...

  • Page 192: Color Modes

    Page 186 Epson Research and Development Vancouver Design Center 12.2 Color Modes 4 Bit-Per-Pixel Color Red Look-Up Table 256x4 0000 0001 0010 0011 0100 0101 0110 4-bit Red Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 Green Look-Up Table 256x4...

  • Page 193: Figure 12-3: 8 Bit-per-pixel Color Mode Data Output Path

    Epson Research and Development Page 187 Vancouver Design Center 8 Bit-Per-Pixel Color Red Look-Up Table 256x4 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Red Data 1111 1000 1111 1001 1111 1010...

  • Page 194: Tv Considerations, Ntsc/pal Operation, Clock Source

    Page 188 Epson Research and Development Vancouver Design Center 13 TV Considerations 13.1 NTSC/PAL Operation NTSC or PAL video is supported in either composite or S-video format. Filters may be enabled to reduce the distortion associated with displaying high resolution computer images on an interlaced TV display.

  • Page 195: Filters, Chrominance Filter (reg[05bh] Bit 5), Luminance Filter (reg[05bh] Bit 4)

    Epson Research and Development Page 189 Vancouver Design Center 13.3 Filters When displaying computer images on a TV, several image distortions are likely to arise: • cross-luminance distortion. • cross-chrominance distortion. • flickering. These distortions are caused by the high-resolution nature of computer images which typically contain sharp color transitions, and sharp luminance transitions (e.g., high...

  • Page 196: Tv Output Levels

    Page 190 Epson Research and Development Vancouver Design Center 13.4 TV Output Levels white yellow cyan green magenta blue black blank sync Figure 13-1: NTSC/PAL SVideo-Y (Luminance) Output Levels Table 13-2: NTSC/PAL SVideo-Y (Luminance) Output Levels NTSC / PAL NTSC / PAL...

  • Page 197: Figure 13-2: Ntsc/pal Svideo-c (chrominance) Output Levels

    Epson Research and Development Page 191 Vancouver Design Center cyan green magenta blue yellow burst blanking burst yellow blue green magenta cyan Figure 13-2: NTSC/PAL SVideo-C (Chrominance) Output Levels Table 13-3: NTSC/PAL SVideo-C (Chrominance) Output Levels NTSC / PAL NTSC / PAL...

  • Page 198

    Page 192 Epson Research and Development Vancouver Design Center cyan yellow green white yellow magenta cyan green yellow magenta blue burst blue cyan black blank green magenta burst sync blue Figure 13-3: NTSC/PAL Composite Output Levels Table 13-4: NTSC/PAL Composite Output Levels...

  • Page 199: Tv Image Display And Positioning

    Epson Research and Development Page 193 Vancouver Design Center 13.5 TV Image Display and Positioning This section describes how to setup and position an image to be displayed on a TV. Figure 13-4: “NTSC/PAL Image Positioning,” on page 194 shows an image positioned on the TV display with the related programmable parameters.

  • Page 200

    Page 194 Epson Research and Development Vancouver Design Center Vertical Sync Field 1, 3 Image t4 / 2 Odd Lines (1, 3, 5, ...) Vertical t5 + 1T Sync LINE Even Field 2, 4 Even Lines (2, 4, 6, ...)

  • Page 201: Tv Cursor Operation

    Epson Research and Development Page 195 Vancouver Design Center Total Display Total Display 752 x 484 920 x 572 Visible Display Visible Display 696 x 436 856 x 518 NTSC Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL Note For most implementations, the visible display does not equal the total display.

  • Page 202: Ink Layer/hardware Cursor Architecture, Ink Layer/hardware Cursor Buffers

    Page 196 Epson Research and Development Vancouver Design Center 14 Ink Layer/Hardware Cursor Architecture 14.1 Ink Layer/Hardware Cursor Buffers The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There may be several Ink Layer/Hardware Cursor images stored in the display buffer but only one may be active at any given time.

  • Page 203: Ink/cursor Data Format

    Epson Research and Development Page 197 Vancouver Design Center 14.2 Ink/Cursor Data Format The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the Ink/Cursor data format for a little endian system. 2-bpp: bit 7 bit 0 Byte 0...

  • Page 204: Ink/cursor Image Manipulation, Ink Image, Cursor Image

    Page 198 Epson Research and Development Vancouver Design Center 14.3 Ink/Cursor Image Manipulation 14.3.1 Ink Image The Ink image should always start at the top left pixel, i.e. Cursor X Position and Cursor Y Position registers should always be set to zero. The width and height of the ink image are automatically calculated to completely cover the display.

  • Page 205

    Epson Research and Development Page 199 Vancouver Design Center P(-x;-y) P(0;0) P(63-x;63-y) Figure 14-3: Clipped Cursor Positioning where For LCD: x = (REG[073h] bits [1:0], REG[072h]) <= 63 and REG[073h] bit 7 = 1 y = (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit 7 = 1 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit 7 = 1...

  • Page 206: Concept

    90° SwivelView™. The display is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13506 in the following sense: A–B–C–D. The S1D13506 rotates and stores the application image in the following sense: C–A–D–B, the same sense as display refresh.

  • Page 207: Register Programming

    Epson Research and Development Page 201 Vancouver Design Center 1024 pixels 1024 pixels display start address portrait window Rotated image in the display buffer Image seen by the user Figure 15-1: Relationship Between Screen Image and 90° Rotated Image in the Display Buffer...

  • Page 208

    Page 202 Epson Research and Development Vancouver Design Center LCD/CRT Memory Address Offset (words) = 1024 for 15/16 bpp mode = 512 for 8 bpp mode Display Start Address As seen in Figure 15-1: “Relationship Between Screen Image and 90° Rotated Image in the Display Buffer,”...

  • Page 209: Physical Memory Requirement

    The following table summarizes the DRAM size requirement for 90° SwivelView™ for different panel sizes and display modes. Note that DRAM size for the S1D13506 is limited to either 512K byte or 2M byte. The calculation is based on the minimum required image buffer size and the Dual Panel Buffer size.

  • Page 210: Limitations

    Page 204 Epson Research and Development Vancouver Design Center Table 15-1: Minimum DRAM Size Required for SwivelView™ Display Min. Image Dual Panel Minimum Ink/Cursor Ink/Cursor Panel Size Panel Type Mode Buffer Size Buffer Size DRAM Size Buffer Size Location 8 bpp...

  • Page 211

    Epson Research and Development Page 205 Vancouver Design Center 15.3 180° SwivelView™ 180° SwivelView™ is accomplished by fetching the display buffer image in the reverse address direction, starting at the bottom-right corner of the image. Unlike 90° SwivelView™, the 180° SwivelView™ image is not rotated in the display buffer. The image is simply displayed 180°...

  • Page 212

    Page 206 Epson Research and Development Vancouver Design Center 15.3.2 Limitations The following limitations apply to 180° SwivelView™: • Hardware Cursor and Ink Layer images are not rotated – software rotation must be used. • CRT/TV mode is not supported.

  • Page 213

    Epson Research and Development Page 207 Vancouver Design Center Display Start Address The Display Start Address must be programmed to be at the bottom-right corner of the image, since the display is now refreshed in the reverse direction. The LCD Display Start Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly.

  • Page 214

    Page 208 Epson Research and Development Vancouver Design Center 15.4.3 Limitations The following limitations apply to 270° SwivelView™: • Only 8/15/16 bpp modes are supported – 4 bpp mode is not supported. • Hardware Cursor and Ink Layer images are not rotated – software rotation must be used.

  • Page 215: Epson Independent Simultaneous Display (eisd), Introduction, Epson Independent Simultaneous Display (eisd)

    16 EPSON Independent Simultaneous Display (EISD) 16.1 Introduction EPSON Independent Simultaneous Display (EISD) allows the S1D13506 to display independent images on two different displays (LCD panel and CRT or TV). The LCD panel timings and mode setup are programmed through the Panel Configuration Registers (REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]).

  • Page 216: Bandwidth Limitation

    When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth available to the S1D13506. The result is that display modes with a high resolution or color depth may not be supported. In some cases, Ink Layers may not be possible on one or both of the displays.

  • Page 217: Mediaplug Interface, Revision Code, How To Enable The Mediaplug Slave

    Page 211 Vancouver Design Center 17 MediaPlug Interface Winnov's MediaPlug Slave interface has been incorporated into the S1D13506. The MediaPlug Slave follows the Specification For Winnov MediaPlug Slave, Local module, Document Rev 0.3 with the following exceptions. 17.1 Revision Code The MediaPlug Slave Revision Code can be determined by reading bits 11:8 of the LCMD register.

  • Page 218: Clocking, Frame Rate Calculation, Lcd Frame Rate Calculation

    Page 212 Epson Research and Development Vancouver Design Center 18 Clocking 18.1 Frame Rate Calculation 18.1.1 LCD Frame Rate Calculation The maximum LCD frame rate is calculated using the following formula. LCD PCLK max. LCD Frame Rate --------------------------------------------------------------------------------------------------------- - ...

  • Page 219: Crt Frame Rate Calculation

    Epson Research and Development Page 213 Vancouver Design Center 18.1.2 CRT Frame Rate Calculation The maximum CRT frame rate is calculated using the following formula. CRT PCLK max. CRT Frame Rate --------------------------------------------------------------------------------------------------------- - × CHDP CHNDP CVDP CVNDP Where: CRT PCLKmax= maximum CRT pixel clock frequency...

  • Page 220: Tv Frame Rate Calculation

    Page 214 Epson Research and Development Vancouver Design Center 18.1.3 TV Frame Rate Calculation The maximum TV frame rate is calculated using the following formula. TV PCLK max. TV Frame Rate ---------------------------------------------------------------------------------------------------------------------- - × THDP THNDP TVDP TVNDP Where: TV PCLKmax= maximum TV pixel clock frequency...

  • Page 221: Example Frame Rates, Frame Rates For 640x480 With Eisd Disabled

    Epson Research and Development Page 215 Vancouver Design Center 18.2 Example Frame Rates For all example frame rates the following conditions apply: • Dual panel buffer is enabled for dual panel. • TV flicker filter is enabled for TV. • MCLK is 40MHz.

  • Page 222: Frame Rates For 800x600 With Eisd Disabled

    Page 216 Epson Research and Development Vancouver Design Center Table 18-1: Frame Rates for 640x480 with EISD Disabled (Continued) Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP VNDP Frame LCD Type PCLK HNDP VNDP Rate Rate (lines) (MHz) (pixels) (MHz)

  • Page 223: Frame Rates For Lcd And Crt (640x480) With Eisd Enabled

    Epson Research and Development Page 217 Vancouver Design Center 18.2.3 Frame Rates for LCD and CRT (640x480) with EISD Enabled Table 18-3: Frame Rates for LCD and CRT (640x480) with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK( HNDP...

  • Page 224: Frame Rates For Lcd And Crt (800x600) With Eisd Enabled

    Page 218 Epson Research and Development Vancouver Design Center 18.2.4 Frame Rates for LCD and CRT (800x600) with EISD Enabled Table 18-4: Frame Rates for LCD and CRT (800x600) with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...

  • Page 225: Frame Rates For Lcd And Ntsc Tv With Eisd Enabled

    Epson Research and Development Page 219 Vancouver Design Center 18.2.5 Frame Rates for LCD and NTSC TV with EISD Enabled Table 18-5: Frame Rates for LCD and NTSC TV with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...

  • Page 226: Frame Rates For Lcd And Pal Tv With Eisd Enabled

    Page 220 Epson Research and Development Vancouver Design Center 18.2.6 Frame Rates for LCD and PAL TV with EISD Enabled Table 18-6: Frame Rates for LCD and PAL TV with EISD Enabled Horiz Vert Horiz Vert Frame CRT/ PCLK HNDP...

  • Page 227: Display Modes, Power Save Mode, Power Save Status Bits

    Additionally, the S1D13506 has a software initiated power save mode. 19.1 Display Modes The S1D13506 resets with both displays inactive, i.e. neither the LCD nor CRT/TV pipelines are active. The displays are independently enabled/disabled by REG[1FCh] bits 2-0: the CRT/TV is instantaneously enabled/disabled by these bits; the LCD is powered up/down according to the sequences in Section 7.4, “Power Sequencing”...

  • Page 228: Power Save Mode Summary

    Page 222 Epson Research and Development Vancouver Design Center 19.4 Power Save Mode Summary Table 19-1: Power Save Mode Summary Power Save Mode Function LCD Disabled CRT/TV Disabled Enabled LCD Display Active? CRT/TV Display Active? Register Access Possible? Memory Access Possible?

  • Page 229: Clocks, Clock Selection

    Epson Research and Development Page 223 Vancouver Design Center 20 Clocks 20.1 Clock Selection The following diagram provides a logical representation of the S1D13506 internal clocks. CLKI BUSCLK BCLK CLKI2 ÷2 MD12 at RESET# MCLK ÷2 REG[010h] bit 0 REG[010h] bit 4 ÷2...

  • Page 230: Clock Descriptions, Mclk, Lcd Pclk, Crt/tv Pclk, Mediaplug Clock

    Vancouver Design Center 20.2 Clock Descriptions 20.2.1 MCLK MCLK should be configured as close to its maximum (40MHz) as possible. The S1D13506 contains sophisticated clock management, therefore, very little power is saved by reducing the MCLK frequency. The frequency of MCLK is directly proportional to the bandwidth of the video memory.

  • Page 231: Clocks Vs. Functions

    Vancouver Design Center 20.3 Clocks vs. Functions The S1D13506 has five clock signals. Not all clock signals must be active for certain chip functions to be carried out. The following table shows which clocks are required for each chip function.

  • Page 232: Mechanical Data

    Page 226 Epson Research and Development Vancouver Design Center 21 Mechanical Data Unit: mm 128-pin QFP15 surface mount package 16.0 ± 0.4 14.0 ± 0.1 Index 0.16 ± 0.1 0~10° 0.5 ± 0.2 Figure 21-1: Mechanical Drawing QFP15 S1D13506 Hardware Functional Specification...

  • Page 233: Sales And Technical Support, Temasek Avenue #36-00

    Epson Research and Development Page 227 Vancouver Design Center 22 Sales and Technical Support Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd. 421-8, Hino, Hino-shi San Jose, CA 95134, USA 10F, No.

  • Page 234

    Page 228 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...

  • Page 235: Programming Notes And Examples

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 236

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...

  • Page 237: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........11 Initialization .

  • Page 238: Table Of Contents

    SwivelView™ ........56 S1D13506 SwivelView ......56 Registers .

  • Page 239: Table Of Contents

    12.2 Considerations ......100 13 Identifying the S1D13506 ....... . 101 14 Hardware Abstraction Layer (HAL) .

  • Page 240

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...

  • Page 241

    List of Tables Table 2-1: S1D13506 Initialization Sequence ......12 Table 4-1: Look-Up Table Configurations ......20 Table 4-2: Suggested LUT Values to Simulate VGA Default 16 Color Palette .

  • Page 242

    Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...

  • Page 243

    Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Pixel Storage for 4 Bpp in One Byte of Display Buffer ....16 Figure 3-2: Pixel Storage for 8 Bpp in One Byte of Display Buffer .

  • Page 244

    Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Programming Notes and Examples X25B-G-003-04 Issue Date: 02/03/21...

  • Page 245

    This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to simplify the programming of the S1D13506. Most S1D1350x and S1D1370x products have HAL support, thus allowing OEMs to do multiple designs with a common code base.

  • Page 246

    2 Initialization This section describes how to initialize the S1D13506. Sample code for performing initial- ization of the S1D13506 is provided in the file init13506.c which is available on the internet at www.eea.epson.com. S1D13506 initialization can be broken into three steps.

  • Page 247

    Epson Research and Development Page 13 Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also Program the Frame Buffer Memory Configuration [020h] 0000 0000 Registers. [021h] 0000 0110 see REG[020h] - REG[02Bh] for details [02Ah]...

  • Page 248

    Page 14 Epson Research and Development Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also [060h] 0000 0000 Program the CRT/TV Display Output Format and Configuration Registers including the FIFOs. [062h] 0000 0000 [063h] 0000 0000 For this example, these values are = don’t care.

  • Page 249

    Epson Research and Development Page 15 Vancouver Design Center Table 2-1: S1D13506 Initialization Sequence (Continued) Register Value Notes See Also [100h] 0000 0000 Program the 2D acceleration (BitBLT) registers to a known state. [101h] 0000 0000 [102h] 0000 0000 [103h]...

  • Page 250: Memory Models, Display Buffer Location, Memory Organization For 4 Bpp (16 Colors/16 Gray Shades)

    3.1 Display Buffer Location The S1D13506 supports either a 512k byte or 2M byte display buffer. The display buffer is memory mapped and is accessible directly by software. The memory block location assigned to the S1D13506 display buffer varies with each individual hardware platform.

  • Page 251: Memory Organization For 8 Bpp (256 Colors/16 Gray Shades)

    Figure 3-3: Pixel Storage for 15 Bpp in Two Bytes of Display Buffer At a color depth of 15 bpp the S1D13506 is capable of displaying 32768 colors. The 32768 color pixel is divided into four parts: one reserved bit, five bits for red, five bits for green, and five bits for blue.

  • Page 252: Memory Organization For 16 Bpp (65536 Colors/64 Gray Shades)

    Figure 3-4: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At a color depth of 16 bpp the S1D13506 is capable of displaying 65536 colors. The 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue.

  • Page 253: Look-up Table (lut)

    For a discussion of the LUT architecture, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. The S1D13506 is designed with a separate LUT for both the LCD and CRT/TV. Each LUT consists of 256 indexed red/green/blue entries. Each LUT entry is four bits wide. The color depth determines how many indices are used to output the image to the display.

  • Page 254: Look-up Table Organization

    This intensity can range in value between 0 and 0Fh. • The S1D13506 Look-Up Table is linear. This means increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh in the red bank results in bright red output while a LUT entry of 05h results in dull red.

  • Page 255

    4 bpp color When the S1D13506 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT.

  • Page 256

    VGA RAMDAC and the S1D13506 LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT level 1...). Additionally, the significant bits of the color tables are located at different offsets within their respective bytes.

  • Page 257

    Epson Research and Development Page 23 Vancouver Design Center Table 4-3: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) Index Index Index Index 15 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not required.

  • Page 258: Gray Shade Modes

    Page 24 Epson Research and Development Vancouver Design Center 4.2.2 Gray Shade Modes This discussion of gray shade (monochrome) modes only applies to the panel interface. Monochrome mode is selected when REG[030h] bit 2 returns a 0. In this mode the value output to the panel is derived solely from the green component of the LUT.

  • Page 259

    Epson Research and Development Page 25 Vancouver Design Center 8 bpp gray shade The 8 bpp gray shade mode uses the green component of the first 16 LUT entries. The green portion of the LUT provides 16 possible intensities. There is no increase in gray shades when selecting 8 bpp mode over 4 bpp mode;...

  • Page 260: Virtual Displays

    Page 26 Epson Research and Development Vancouver Design Center 5 Virtual Displays This section discusses the concept of a virtual display and covers navigation within a virtual display using panning and scrolling. 5.1 Virtual Display Virtual display is where the image to be viewed is larger than the physical display. This can be in the horizontal, vertical or both dimensions.

  • Page 261

    Epson Research and Development Page 27 Vancouver Design Center 5.1.1 Registers REG[046h] LCD Memory Address Offset Register 0 LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory LCD Memory Address Address Address Address Address Address...

  • Page 262

    “virtual” image. After determining the amount of memory used by each line (see example 1), calculate whether there is enough memory to support the desired number of lines. 1. Initialize the S1D13506 registers for a 640x480 panel. (See Section 2, “Initialization” on page 12). 2. Calculate the number of pixels per word.

  • Page 263

    Epson Research and Development Page 29 Vancouver Design Center = PixelsPerVirtualLine ÷ PixelsPerWord Offset = 800 ÷ 4 = 200 words = 0C8h words For the LCD, REG[047h] is set to 00h and REG[046h] is set to C8h. For the CRT/TV, REG[067h] is set to 00h and REG[066h] is set to C8h.

  • Page 264: Panning And Scrolling

    The pixel pan registers (REG[048h] for LCD, REG[068h] for CRT/TV) allow panning in smaller increments than changing the start address alone. Internally, the S1D13506 latches different signals at different times. Due to this internal sequence, the start address and pixel pan registers should be accessed in a specific order during panning and scrolling operations, in order to provide the smoothest scrolling.

  • Page 265

    Epson Research and Development Page 31 Vancouver Design Center 5.2.1 Registers REG[042h] LCD Display Start Address Register 0 LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display Start Address Start Address Start Address...

  • Page 266

    Page 32 Epson Research and Development Vancouver Design Center REG[048h] LCD Pixel Panning Register LCD Pixel LCD Pixel Reserved Reserved Panning Bit 1 Panning Bit 0 REG[068h] CRT/TV Pixel Panning Register CRT/TV Pixel CRT/TV Pixel Reserved Reserved Panning Bit 1...

  • Page 267

    Epson Research and Development Page 33 Vancouver Design Center When panning to the left on an LCD set for a color depth of 4 bpp, the registers would be updated as follows. 1. Pan left by 1 pixel - decrement the pixel panning register by 1: REG[048h] = 11b.

  • Page 268

    Page 34 Epson Research and Development Vancouver Design Center StartAddress = PanValue SHR 2 (remove PixelPan bits) 3. Write the pixel panning and start address register values using the procedure outlined in Section 5.2.1, “Registers” on page 31. Example 4: Scrolling - Up and Down...

  • Page 269: Enabling Power Save Mode

    6 Power Save Mode The S1D13506 has been designed for very low-power applications. During normal operation, the internal clocks are dynamically disabled when not required. The S1D13506 design also includes a Power Save Mode to further save power. When Power Save Mode is initiated, automatic LCD power sequencing takes place to ensure the LCD bias power supply is disabled properly.

  • Page 270

    The Memory Controller Power Save Status bit is a read-only status bit which indicates the power save state of the S1D13506 DRAM interface. When this bit returns a 1, the DRAM interface is powered down (the DRAM is either in self-refresh mode or completely idle).

  • Page 271: Dram Refresh Selection

    Epson Research and Development Page 37 Vancouver Design Center 6.2.3 DRAM Refresh Selection REG[021h] DRAM Refresh Rate Register DRAM DRAM DRAM Refresh Refresh Refresh Rate Refresh Rate Refresh Rate Select Bit 1 Select Bit 0 Bit 2 Bit 1 Bit 0 The Refresh Select bits specify the type of DRAM refresh used while Power Save Mode is enabled.

  • Page 272: Automatic Sequencing, Manual Sequencing

    This section assumes the LCD bias power is controlled through GPIO1. The S1D13506 GPIO pins are multi-use pins and may not be available in all system designs. For further information on the availability of GPIO pins, see the S1D13506 Hardware Functional Specification, document number X25B-B-001-xx.

  • Page 273: Enabling The Lcd Panel, Disabling The Lcd Panel

    7.2.2 Enabling the LCD Panel If the LCD bias power supply timing requirements are different than those timings built into the S1D13506 automated LCD power sequencing, it may be necessary to manually enable the LCD panel. In such a case, the following procedure applies.

  • Page 274: Hardware Cursor/ink Layer

    8 Hardware Cursor/Ink Layer 8.1 Introduction The S1D13506 supports either a Hardware Cursor or an Ink Layer for the LCD, and either a Hardware Cursor or an Ink Layer for the CRT/TV. The LCD and CRT/TV are supported independently, so it is possible to select combinations such as a Hardware Cursor on the LCD and an Ink Layer on the CRT/TV.

  • Page 275

    Epson Research and Development Page 41 Vancouver Design Center 8.2 Registers REG[070h] LCD Ink/Cursor Control Register Ink/Cursor Ink/Cursor Mode Bit 1 Mode Bit 0 REG[080h] CRT/TV Ink/Cursor Control Register CRT/TV CRT/TV Ink/Cursor Ink/Cursor Mode Bit 1 Mode Bit 0 The Ink/Cursor mode bits determine which of the Hardware Cursor or Ink Layer is active as shown in following table.

  • Page 276

    Page 42 Epson Research and Development Vancouver Design Center REG[072h] LCD Cursor X Position Register 0 LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X...

  • Page 277

    Epson Research and Development Page 43 Vancouver Design Center REG[074h] LCD Cursor Y Position Register 0 LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y...

  • Page 278

    Page 44 Epson Research and Development Vancouver Design Center REG[076h] LCD Ink/Cursor Blue Color 0 Register Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Bit 4 Bit 3...

  • Page 279

    Epson Research and Development Page 45 Vancouver Design Center REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0 Blue Color 0...

  • Page 280

    Page 46 Epson Research and Development Vancouver Design Center REG[07Eh] LCD Ink/Cursor FIFO High Threshold Register Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor FIFO High FIFO High FIFO High FIFO High Threshold Threshold Threshold Threshold Bit 3 Bit 2 Bit 1 Bit 0...

  • Page 281: Memory Considerations

    Page 47 Vancouver Design Center 8.3 Initialization This section describes the process of initializing the S1D13506 for a Hardware Cursor or Ink Layer. 8.3.1 Memory Considerations Both the Hardware Cursor and Ink Layer are positioned in the display buffer by the LCD Ink/Cursor Start Address register (REG[071h]) and CRT/TV Ink/Cursor Start Address register (REG[081h]).

  • Page 282

    Page 48 Epson Research and Development Vancouver Design Center 8.3.2 Examples Example 5: Initializing the Hardware Cursor The following example places an LCD Hardware Cursor at the end of a 2M byte display buffer. SwivelView™ modes require software rotation of the Ink Layer. This can only occur when a Dual Panel Buffer is not required.

  • Page 283

    Epson Research and Development Page 49 Vancouver Design Center Example 6: Initializing the Ink Layer The following example places an Ink Layer at the end of a 2M byte display buffer. SwivelView™ modes require software rotation of the Ink Layer. Color 0 is set to black, and color 1 is set to white.

  • Page 284: Writing Cursor/ink Layer Images, Hardware Cursor/ink Layer Data Format

    Page 50 Epson Research and Development Vancouver Design Center 8.4 Writing Cursor/Ink Layer Images This section describes how to write images to the Hardware Cursor and Ink Layer. The Hardware Cursor is a 64x64 image at a color depth of 2 bpp. The Ink Layer is the same size as the virtual display (width x height) at a color depth of 2 bpp.

  • Page 285

    Epson Research and Development Page 51 Vancouver Design Center 8.4.2 Cursor Image The following procedures demonstrate how to write an image to the Hardware Cursor buffer. Landscape Mode (no rotation) 1. For the LCD cursor, calculate the start address based on the value in REG[071h].

  • Page 286: Ink Layer Image

    Page 52 Epson Research and Development Vancouver Design Center 8.4.3 Ink Layer Image The following procedures demonstrate how to write an image to the Ink Layer buffer. Landscape Mode (no rotation) 1. For the LCD, calculate the start address based on the value in REG[071h].

  • Page 287: Cursor Movement, Move Cursor In Landscape Mode (no Rotation)

    Epson Research and Development Page 53 Vancouver Design Center 8.5 Cursor Movement The following section discusses cursor movement in landscape, SwivelView 90°, SwivelView 180°, and SwivelView 270° modes. It is possible to move the top left corner of the cursor to a negative position (-63, -63). This allows the cursor to be clipped (only a portion is visible on-screen).

  • Page 288: Move Cursor In Swivelview 90° Rotation, Move Cursor In Swivelview 180° Rotation

    Page 54 Epson Research and Development Vancouver Design Center 8.5.2 Move Cursor in SwivelView 90° Rotation In the following example, (x, y) represent the desired cursor position. 1. Calculate abs(x), the absolute (non-negative) value of x. 2. Write the least significant byte of abs(x) to Y Position Register 0.

  • Page 289: Move Cursor In Swivelview 270° Rotation

    Epson Research and Development Page 55 Vancouver Design Center 8.5.4 Move Cursor in SwivelView 270° Rotation In the following example, (x, y) represent the desired cursor position. 1. Calculate the value of x2, where x2 = display width - x - 64 2.

  • Page 290: S1d13506 Swivelview

    SwivelView 90° or SwivelView 270° rotates to a landscape orientation. 9.1 S1D13506 SwivelView The S1D13506 provides hardware support for SwivelView in 8, 15 and 16 bpp color depths on LCD panels. SwivelView is not supported on CRT or TV displays.

  • Page 291

    Epson Research and Development Page 57 Vancouver Design Center Table 9-1: SwivelView Enable Bits SwivelView Enable SwivelView Enable Display Rotated Bit 1 Bit 0 (degrees) REG[046h] LCD Memory Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4...

  • Page 292

    Page 58 Epson Research and Development Vancouver Design Center REG[042h] LCD Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[043h] LCD Display Start Address Register 1 Bit 15...

  • Page 293

    9.4 Examples Source code demonstrating various SwivelView rotations is provided in the file 13506swivel.c available on the internet at www.eea.epson.com. Example 7: Rotate Image 90° for a 640x480 display at a color depth of 8 bpp. Before enabling SwivelView, the display buffer should be cleared. This makes the transition smoother as existing display images cannot be rotated by hardware - a repaint is necessary.

  • Page 294: Simultaneous Display Considerations

    Page 60 Epson Research and Development Vancouver Design Center Program the LCD Display Start Address Registers. REG[044h] is set to 04h, REG[043h] is set to AFh, and REG[042h] is set to FFh. 3. Set SwivelView Bit 1 by setting bit 4 of REG[040h] 4.

  • Page 295

    CPU. The 2D BitBLT Engine in the S1D13506 is designed to increase the speed of the most common GUI operations by off-loading work from the CPU, thus reducing traffic on the system bus and improving the efficiency of the display buffer interface.

  • Page 296

    Page 62 Epson Research and Development Vancouver Design Center REG[100h] BitBLT Control Register 0 BitBLT FIFO BitBLT FIFO BitBLT FIFO BitBLT BitBLT BitBLT Active Not Empty Half Full Full Status Destination Source Linear Status Status (RO) Status (RO) (RO) Linear Select Select The BitBLT FIFO Not Empty Status bit is a read-only status bit.

  • Page 297

    Epson Research and Development Page 63 Vancouver Design Center REG[101h] BitBLT Control Register 1 BitBLT Color Reserved Format Select This bit is reserved and must be set to 0. REG[101h] BitBLT Control Register 1 BitBLT Color Reserved Format Select The BitBLT Color Format Select bit selects the color format that the BitBLT operation is applied to.

  • Page 298

    Page 64 Epson Research and Development Vancouver Design Center REG[103h] BitBLT Operation Register BitBLT BitBLT BitBLT BitBLT Operation Operation Operation Operation Bit 3 Bit 2 Bit 1 Bit 0 The BitBLT Operation Register selects the BitBLT operation to be carried out based on the...

  • Page 299

    Epson Research and Development Page 65 Vancouver Design Center If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word and the other address bits are ignored. In pattern fill operation, the BitBLT Source Start Address is defined by the following equation: Source Start Address Register = Pattern Base Address + Pattern Line Offset + Pixel Offset.

  • Page 300

    Page 66 Epson Research and Development Vancouver Design Center REG[10Ch] BitBLT Memory Address Offset Register 0 BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address...

  • Page 301

    Epson Research and Development Page 67 Vancouver Design Center REG[114h] BitBLT Background Color Register 0 BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Background Background Background Background Background Background Background Background Color Color Color Color Color Color Color Color Bit 7...

  • Page 302: Bitblt Descriptions

    While the FIFO is being written to by the CPU, it is also being emptied by the S1D13506. If the S1D13506 empties the FIFO faster than the CPU can fill it, it may not be possible to cause an overflow/underflow. In these cases, performance can be improved by not monitoring the FIFO status.

  • Page 303: Write Blit With Rop

    Epson Research and Development Page 69 Vancouver Design Center 10.2.1 Write Blit with ROP The Write Blit increases the speed of transferring data from system memory to the display buffer. The Write Blit with ROP fills a specified area of the display buffer with data supplied by the CPU.

  • Page 304

    Page 70 Epson Research and Development Vancouver Design Center Example 9: Write a 100 x 20 rectangle at the screen coordinates x = 25, y = 38 using a 640x480 display at a color depth of 8 bpp. 1. Calculate the destination address (upper left corner of the screen blit rectangle) using the following formula.

  • Page 305: Color Expand Bitblt

    Epson Research and Development Page 71 Vancouver Design Center 10. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (Bit- BLT Destination Linear Select = 0, BitBLT Source Linear Select = 0). Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h, then wait until REG[100h] bit 7 returns a 1.

  • Page 306

    Page 72 Epson Research and Development Vancouver Design Center Partially “masked” color expand BitBLT can be used when drawing a portion of a pattern (i.e. a portion of a character) on the screen. The following examples illustrate how one WORD is expanded using the Color Expand BitBLT.

  • Page 307

    Epson Research and Development Page 73 Vancouver Design Center Source Address = 0 Start Bit Position = 0 Blit Width = 3 The following bits are expanded. Word Sent To BitBLT Engine High Byte Low Byte All subsequent WORDS in one blit line are then serially expanded starting at bit 7 of the low byte until the end of the blit line.

  • Page 308

    Page 74 Epson Research and Development Vancouver Design Center where: = (BitmapWidth + 15) ÷ 16 SourceStride = (300 + 15) ÷ 16 = 19 WORDS per line = 38 BYTES per line 2. Calculate the destination address (upper left corner of the screen blit rectangle) using the following formula.

  • Page 309

    Epson Research and Development Page 75 Vancouver Design Center 9. Program the Foreground Color Registers to the foreground color. REG[119h] is set to 00h and REG[118h] is set to 86h (134 decimal). Note that for 15/16 bpp color depths REG[119h] and Reg[118h] are both required and programmed directly with the value of the foreground color.

  • Page 310: Color Expand Bitblt With Transparency, Solid Fill Bitblt

    Page 76 Epson Research and Development Vancouver Design Center Note The order of register initialization is irrelevant as long as all relevant registers are pro- grammed before the BitBLT is initiated. 10.2.3 Color Expand BitBLT With Transparency This BitBLT operation is virtually identical to the Color Expand BitBLT, except the background color is completely ignored.

  • Page 311: Move Bitblt In A Positive Direction With Rop

    Epson Research and Development Page 77 Vancouver Design Center 6. Program the BitBLT Color Format Register for 16 bpp operations. REG[101h] is set to 01h. 7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS. BltMemoryOffset = ScreenStride ÷ 2...

  • Page 312

    Page 78 Epson Research and Development Vancouver Design Center Destination Address greater than Source Address Destination Address less than Source Address Use Move BitBLT in Negative Direction Use Move BitBLT in Positive Direction Figure 10-1: Move BitBLT Usage Example 12: Copy a 9 x 321 rectangle at the screen coordinates x = 100, y = 10 to screen coordinates x = 200, y = 20 using a 640x480 display at a color depth of 16 bpp.

  • Page 313: Move Bitblt In Negative Direction With Rop

    Epson Research and Development Page 79 Vancouver Design Center 5. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h] is set to 0Ch. 6. Program the BitBLT Color Format Select bit for 16 bpp operations. REG[101h] is set to 01h.

  • Page 314

    Page 80 Epson Research and Development Vancouver Design Center DestinationAddress = ((Y + Height - 1) × ScreenStride) + ((X + Width - 1) × BytesPerPixel) = ((20 + 321 - 1) × (640 × 2)) + ((105 + 9 - 1) × 2)

  • Page 315: Transparent Write Blit

    Epson Research and Development Page 81 Vancouver Design Center 10.2.7 Transparent Write Blit The Transparent Write Blit increases the speed of transferring data from system memory to the display buffer. Once the Transparent Write Blit begins, the blit engine remains active until all pixels have been written.

  • Page 316

    Page 82 Epson Research and Development Vancouver Design Center DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel) = (38 × 640) + (25 × 1) = 24345 = 5F19h where: BytesPerPixel = 1 for 8 bpp BytesPerPixel = 2 for 15/16 bpp ScreenStride = DisplayWidthInPixels ×...

  • Page 317: Transparent Move Bitblt In Positive Direction

    Epson Research and Development Page 83 Vancouver Design Center 10. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (Bit- BLT Destination Linear Select = 0, BitBLT Source Linear Select = 0). Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h, then wait until REG[100h] bit 7 returns a 1.

  • Page 318

    Page 84 Epson Research and Development Vancouver Design Center Example 15: Copy a 9 x 321 rectangle at the screen coordinates x = 100, y = 10 to screen coordinates X = 200, Y = 20 using a 640x480 display at a color depth of 16 bpp.

  • Page 319: Pattern Fill Bitblt With Rop

    Epson Research and Development Page 85 Vancouver Design Center 8. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (Bit- BLT Destination Linear Select = 0, BitBLT Source Linear Select = 0). Start the blit operation. REG[100h] is set to 80h.

  • Page 320

    Page 86 Epson Research and Development Vancouver Design Center SourceAddress = PatternOffset + StartPatternY × 8 × BytesPerPixel + StartPatternX × BytesPerPixel = 1M + (4 × 8 × 1) + (3 × 1) = 1M + 35 = 1048611...

  • Page 321: Pattern Fill Bitblt With Transparency

    Epson Research and Development Page 87 Vancouver Design Center 10.2.10 Pattern Fill BitBLT with Transparency The Pattern Fill BitBLT with Transparency fills a specified rectangular area of the display buffer with a pattern. When a transparent color is selected, pattern pixels of the transparent color will not get copied, allowing creation of hatched patterns.

  • Page 322: Move Bitblt With Color Expansion

    Page 88 Epson Research and Development Vancouver Design Center where: BytesPerPixel = 1 for 8 bpp BytesPerPixel = 2 for 15/16 bpp Program the BitBLT Source Start Address Registers. REG[106h] is set to 10h, REG[105h] is set to 00h, and REG[104h] is set 23h.

  • Page 323

    Epson Research and Development Page 89 Vancouver Design Center The Move BitBLT with Color Expansion is used to accelerate text drawing on the screen. A monochrome bitmap of a font in off-screen memory occupies very little space and takes advantage of the hardware acceleration. Since the foreground and background colors are programmable, text of any color can be created.

  • Page 324: Transparent Move Blit With Color Expansion, Read Blit

    Page 90 Epson Research and Development Vancouver Design Center 5. Program the BitBLT Operation Register to select the Move Blit with Color Expan- sion. REG[103h] is set to 0Bh. 6. Program the BitBLT Foreground Color Register to select black (in 16 bpp black = 0000h).

  • Page 325

    Epson Research and Development Page 91 Vancouver Design Center For 8 bpp color depths, the formula must take into consideration that the blit engine accepts only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether the first pixel of each line is stored in the low byte or high byte.

  • Page 326: S1d13506 Bitblt Synchronization

    The order of register initialization is irrelevant as long as all relevant registers are pro- grammed before the BitBLT is initiated. 10.3 S1D13506 BitBLT Synchronization A BitBLT operation can only be started if the blit engine is not busy servicing another blit.

  • Page 327

    Epson Research and Development Page 93 Vancouver Design Center Testing the BitBLT Active Status after starting a new BitBLT is simpler and less prone to errors. To test after each BitBLT operation, perform the following. 1. Program and start the blit engine.

  • Page 328: S1d13506 Bitblt Known Limitations

    BitBLT Width must be > 1 for 15/16 bpp color depths and > 2 for 8 bpp. 10.5 Sample Code Sample code demonstrating how to program the S1D13506 BitBLT engine is provided in the file 13506BLT.ZIP. This file is available on the internet at www.eea.epson.com.

  • Page 329: Crt/tv Considerations, Crt Considerations, Generating Crt Timings With 13506cfg, Dac Output Level Selection

    Vancouver Design Center 11 CRT/TV Considerations The S1D13506 is capable of driving an LCD panel, CRT display, or a TV monitor. However, only an LCD panel and CRT or an LCD panel and TV can be driven simulta- neously. It is not possible to drive both a CRT and TV at the same time.

  • Page 330: Ntsc Timings, Pal Timings

    3. Enable the CRT. REG[1FCh] is set to 1. Sample code demonstrating how to enable the CRT display is provided in the file 56_CRT.c. This file is available on the internet at www.eea.epson.com. 11.2 TV Considerations TV timings are based on either the NTSC or PAL specifications. The TV display can be output in either composite video or S-video format.

  • Page 331: Tv Filters

    4). It adjusts the brightness of the TV, reducing the “rainbow-like” colors at the boundaries between sharp brightness transitions. The Luminance Filter may improve the TV picture quality when in composite video format. For further information on the TV filters, see the S1D13506 Hardware Functional Specifi- cation, document number X25B-A-001-xx. 11.2.4 Examples Example 21: Enable the TV display and set the Flicker Filter.

  • Page 332: Simultaneous Display

    This file is available on the internet at www.eea.epson.com. 11.3 Simultaneous Display The S1D13506 supports simultaneous display of an LCD panel and CRT or an LCD panel and TV. Both display images are completely independent. Each display can show separate areas of the display buffer and display different color depths.

  • Page 333

    Winnov. The MediaPlug interface on the S1D13506 must be enabled to function correctly. To enable the MediaPlug interface, MD13 and MD14 must be high (1) on the rising edge of RESET#.

  • Page 334

    MediaPlug interface. Therefore, when the MediaPlug interface is enabled, Color 16-bit panels cannot be used without an external multiplexing circuit. For further information on the external circuit required, see the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. The MediaPlug interface requires a source clock between 8MHz and 19MHz to operate (optimal is 14.318MHz).

  • Page 335: Identifying The S1d

    Vancouver Design Center 13 Identifying the S1D13506 The S1D13506 can only be identified once the Memory/Register Select bit is set to 0. The steps to identify the S1D13506 are: 1. Set the Memory/Register Select bit to 0 by writing 00h to REG[001h].

  • Page 336: Hardware Abstraction Layer (hal), Api For 13506hal

    Note As the S1D13x0x line of products changes, the HAL may change significantly or cease to be a useful tool. Seiko Epson reserves the right to change the functionality of the HAL or discontinue its use if no longer required.

  • Page 337

    Epson Research and Development Page 103 Vancouver Design Center Table 14-1: HAL Functions (Continued) Function Description seDisplayBlank seDisplayLcdBlank Blank/unblank the display by disabling the FIFO. seDisplayCrtBlank seDisplayTvBlank seDisplayEnable seLcdDisplayEnable Enable/disable the display. seCrtDisplayEnable seTvDisplayEnable Advanced HAL Functions: seBeginHighPriority Increase thread priority for time critical routines.

  • Page 338

    Page 104 Epson Research and Development Vancouver Design Center Table 14-1: HAL Functions (Continued) Function Description seReadLutEntry seReadLcdLutEntry Reads one RGB element from the lookup table. seReadCrtLutEntry seReadTvLutEntry seWriteLut seWriteLcdLut Write the entire lookup table. seWriteCrtLut seWriteTvLut seReadLut seReadLcdLut Read the entire lookup table.

  • Page 339

    Epson Research and Development Page 105 Vancouver Design Center Table 14-1: HAL Functions (Continued) Function Description seDrawCircle seDrawLcdCircle Draws a circle of given radius and color at the specified center point. seDrawCrtCircle seDrawTvCircle seDrawEllipse seDrawLcdEllipse Draws an ellipse centered on a given point with the specified horizontal and vertical seDrawCrtEllipse radius.

  • Page 340

    Page 106 Epson Research and Development Vancouver Design Center Table 14-1: HAL Functions (Continued) Function Description seInitInk seInitLcdInk Prepares the hardware ink layer for use. seInitCrtInk seInitTvInk seFreeInk seFreeLcdInk Frees memory allocated to the hardware ink layer. seFreeCrtInk seFreeTvInk seEnableInk seEnableLcdInk Enable (show) or disable (hide) the hardware ink layer.

  • Page 341

    LPHAL_STRUC lpHalInfo) Description: This function registers the S1D13506 device parameters with the HAL library. The device parameters include such item as address range, register values, desired frame rate, and more which are stored in the HAL_STRUCT structure pointed to by lpHalInfo. Addition- ally this routine allocates system memory as address space for accessing registers and the display buffer.

  • Page 342

    Epson Research and Development Vancouver Design Center int seInitReg(unsigned DisplayMode, unsigned Flags) Description: This function initializes the S1D13506 registers, the LUT, assigns default surfaces and allocates memory accordingly. Parameters: DisplayMode Set this parameter according to the type of initialization desired.

  • Page 343

    Page 109 Vancouver Design Center int seGetId(int * pId) Description: Reads the S1D13506 revision code register to determine the controller product and revi- sion. Parameters: A pointer to an integer to receive the controller ID. The value returned is an interpreted version of the controller identification.

  • Page 344: General Hal Support

    Page 110 Epson Research and Development Vancouver Design Center 14.2.1 General HAL Support This category of HAL functions provide several essential services which do not readily group with other functions. DWORD seGetInstalledMemorySize(void) Description: This function returns the size of display buffer memory in bytes.

  • Page 345

    Epson Research and Development Page 111 Vancouver Design Center int seGetResolution(unsigned *Width, unsigned *Height) void seGetLcdResolution(unsigned *Width, unsigned *Height) void seGetCrtResolution(unsigned *Width, unsigned *Height) void seGetTvResolution(unsigned *Width, unsigned *Height) Description: These functions return the width and height of the physical display device. Virtual dimen- sions are not accounted for in the return value.

  • Page 346

    Description: This function retrieves the SwivelView orientation of the LCD display. The SwivelView status is read directly from the S1D13506 registers. Calling this function when the LCD display is not enabled will result in an erroneous return a value. Note Only the LCD interface supports SwivelView.

  • Page 347

    This implies two conditions for proper operation: a) The S1D13506 control registers must be configured to correct values. b) Either the CRT or LCD display interface must be enabled.

  • Page 348

    Page 114 Epson Research and Development Vancouver Design Center void seDisplayEnable(BOOL Enable) void seLcdDisplayEnable(BOOL Enable) void seCrtDisplayEnable(BOOL Enable) void seTvDisplayEnable(BOOL Enable) Description: These functions enable or disable the selected display device. seDisplayEnable() enables or disables the display for the active surface.

  • Page 349: Advance Hal Functions

    Description: Writing and debugging software under the Windows operating system greatly simplifies the developing process for the S1D13506 evaluation system. One issue which impedes application programming is that of latency. Time critical operations, performance mea- surement for instance, are not guaranteed any set amount of processor time.

  • Page 350

    Page 116 Epson Research and Development Vancouver Design Center int seSetClock(CLOCKSELECT ClockSelect, FREQINDEX FreqIndex) Description: Call seSetClock() to set the clock rate of the programmable clock. ClockSelect The ICD2061A programmable clock chip supports two output clock Parameters: signals. ClockSelect chooses which of the two output clocks to adjust.

  • Page 351: Surface Support

    Page 117 Vancouver Design Center 14.2.3 Surface Support The S1D13506 HAL library depends heavily on the concept of surfaces. Through surfaces the HAL tracks memory requirements of the attached display devices, hardware cursor and ink layers, and the Dual Panel buffer.

  • Page 352

    Page 118 Epson Research and Development Vancouver Design Center DWORD seGetSurfaceOffsetAddress(void) Description: This function returns the offset, from the first byte of display memory to the first byte of memory associated with the active display surface. Parameters: None. Return Value: The return value is the offset, in bytes, from the start of display memory to the start of the active surface.

  • Page 353

    Epson Research and Development Page 119 Vancouver Design Center void seSetLcdAsActiveSurface(void) void seSetCrtAsActiveSurface(void) void seSetTvAsActiveSurface(void) Description: These functions set the active surface to the display indicated in the function name. Before calling one of these surface selection routines, that surface must have been allo- cated using any of the surface allocation methods.

  • Page 354: Register Access

    14.2.4 Register Access The Register Access functions provide convenient method of accessing the control registers of the S1D13506 controller using byte, word or dword widths. To reduce the overhead of the function call as much as possible, two steps were taken: •...

  • Page 355

    Epson Research and Development Page 121 Vancouver Design Center void seWriteRegWord(DWORD Index, unsigned Value) Description: This routine writes the word contained in Value to the specified index. Index Offset to the register pair to be written. Parameters: Value The value, in the least significant word, to write to the registers.

  • Page 356: Memory Access

    14.2.5 Memory Access The Memory Access functions provide convenient method of accessing the display memory on an S1D13506 controller using byte, word or dword widths. To reduce the overhead of these function calls as much as possible, two steps were taken: •...

  • Page 357

    Epson Research and Development Page 123 Vancouver Design Center Note If ((Offset + Count) > memory size) then this function limits the writes to the end of dis- play memory. void seWriteDisplayWords(DWORD Offset, unsigned Value, DWORD Count) Description: This routine writes one or more words to display memory starting at the specified offset.

  • Page 358: Color Manipulation

    Page 124 Epson Research and Development Vancouver Design Center 14.2.6 Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look-Up Table directly through the accessor functions and indirectly through the color depth setting functions.

  • Page 359

    Epson Research and Development Page 125 Vancouver Design Center void seReadLutEntry(int Index, BYTE *pRGB) void seReadLcdLutEntry(int Index, BYTE *pRGB) void seReadCrtLutEntry(int Index, BYTE *pRGB) void seReadTvLutEntry(int Index, BYTE *pRGB) ¦Description: These routines read one lookup table entry and return the results in the byte array pointed to by pRGB.

  • Page 360

    Page 126 Epson Research and Development Vancouver Design Center void seReadLut(BYTE *pRGB, int Count) void seReadLcdLut(BYTE *pRGB, int Count) void seReadCrtLut(BYTE *pRGB, int Count) void seReadTvLut(BYTE *pRGB, int Count) ¦Description: This routine reads one or more lookup table entries and returns the result in the array pointed to by pRGB.

  • Page 361

    Epson Research and Development Page 127 Vancouver Design Center seSetLcdCrtBitsPerPixel() and seSetLcdTvBitsPerPixel() change the color depth for a sur- face which combines LCD and CRT/TV. Portrait (SwivelView 90) is disabled. If the dis- play resolution is not the same for the two displays then memory is allocated based on the larger of the two.

  • Page 362

    Width, DWORD Height) Description: These functions prepare the S1D13506 for displaying a virtual image. “Virtual Image” describes the condition where the image contained in display memory is larger than the physical display. In this situation the display surface is used as a window into the larger display memory area.

  • Page 363

    Epson Research and Development Page 129 Vancouver Design Center void seVirtPanScroll(DWORD x, DWORD y) void seLcdVirtPanScroll(DWORD x, DWORD y) void seCrtVirtPanScroll(DWORD x, DWORD y) void seTvVirtPanScroll(DWORD x, DWORD y) void seLcdCrtVirtPanScroll(DWORD x, DWORD y) void seLcdTvVirtPanScroll(DWORD x, DWORD y) Description: When displaying a virtual image the display surface is smaller than the virtual image con- tained in display memory.

  • Page 364

    Page 130 Epson Research and Development Vancouver Design Center 14.2.8 Drawing Functions in this category perform primitive drawing on the specified display surface. Supported drawing primitive include pixels, lines, rectangles, ellipses and circles. void seSetPixel(long x, long y, DWORD Color)

  • Page 365

    Epson Research and Development Page 131 Vancouver Design Center DWORD seGetPixel(long x, long y) DWORD seGetLcdPixel(long x, long y) DWORD seGetCrtPixel(long x, long y) DWORD seGetTvPixel(long x, long y) Description: Returns the pixel color at the specified display location Use seGetPixel() to read the pixel color at the specified x,y co-ordinates on the current active surface.

  • Page 366

    Page 132 Epson Research and Development Vancouver Design Center void seDrawLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawLcdLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawCrtLine(long x1, long y1, long x2, long y2, DWORD Color)

  • Page 367

    Epson Research and Development Page 133 Vancouver Design Center void seDrawRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) void seDrawLcdRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) void seDrawCrtRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill)

  • Page 368

    Page 134 Epson Research and Development Vancouver Design Center void seDrawCircle(long xCenter, long yCenter, long Radius, DWORD Color) void seDrawLcdCircle(long xCenter, long yCenter, long Radius, DWORD Color) void seDrawCrtCircle(long xCenter, long yCenter, long Radius, DWORD Color) void seDrawTvCircle(long xCenter, long yCenter, long Radius, DWORD Color) Description: These routines draw a circle on the screen in the specified color.

  • Page 369

    Epson Research and Development Page 135 Vancouver Design Center void seDrawEllipse(long xc, long yc, long xr, long yr, DWORD Color) void seDrawLcdEllipse(long xc, long yc, long xr, long yr, DWORD Color) void seDrawCrtEllipse(long xc, long yc, long xr, long yr, DWORD Color)

  • Page 370: Hardware Cursor

    The same S1D13506 uses the same hardware for both hardware cursor and ink layer which means that only the cursor or the ink layer can be active at any given time.The difference...

  • Page 371

    Epson Research and Development Page 137 Vancouver Design Center void seFreeCursor(void) void seFreeLcdCursor(void) void seFreeCrtCursor(void) void seFreeTvCursor(void) Description: These functions release memory allocated to the hardware cursor by seInitCursor() func- tions. Use seFreeCursor() to free the hardware cursor memory for the current active surface.

  • Page 372

    Page 138 Epson Research and Development Vancouver Design Center DWORD seGetCursorLinearAddress(void) DWORD seGetLcdCursorLinearAddress(void) DWORD seGetCrtCursorLinearAddress(void) DWORD seGetTvCursorLinearAddress(void) Description: These routines return address for the hardware cursor through which the application can directly access the cursor memory. Call seGetCursorLinearAddress() to retrieve the address of the hardware cursor associated with the current active surface.

  • Page 373

    Epson Research and Development Page 139 Vancouver Design Center void seMoveCursor(long x, long y) void seMoveLcdCursor(long x, long y) void seMoveCrtCursor(long x, long y) void seMoveTvCursor(long x, long y) Description: These routines are move where the hardware cursor is shown on the display surface.

  • Page 374

    Page 140 Epson Research and Development Vancouver Design Center void seSetCursorPixel(long x, long y, DWORD Color) void seSetLcdCursorPixel(long x, long y, DWORD Color) void seSetCrtCursorPixel(long x, long y, DWORD Color) void seSetTvCursorPixel(long x, long y, DWORD Color) Description: These functions are intended for drawing in the hardware cursor area a pixel at a time.

  • Page 375

    Epson Research and Development Page 141 Vancouver Design Center void seDrawCursorLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawLcdCursorLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawCrtCursorLine(long x1, long y1, long x2, long y2, DWORD Color)

  • Page 376

    Page 142 Epson Research and Development Vancouver Design Center void seDrawCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFIll) void seDrawLcdCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill) void seDrawCrtCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)

  • Page 377: Ink Layer

    The same S1D13506 uses the same hardware for both hardware cursor and ink layer which means that only the cursor or the ink layer can be active at any given time.The difference...

  • Page 378

    Page 144 Epson Research and Development Vancouver Design Center void seFreeInk(void) void seFreeLcdInk(void) void seFreeCrtInk(void) void seFreeTvInk(void) Description: These functions release the memory allocations made by the call to the seInitInk() calls. Prior to calling the seFreeInk() functions the application must make a call to seEn- ableInk() to hide the ink layer.

  • Page 379

    Epson Research and Development Page 145 Vancouver Design Center DWORD seGetInkLinearAddress(void) DWORD seGetLcdInkLinearAddress(void) DWORD seGetCrtInkLinearAddress(void) DWORD seGetTvInkLinearAddress(void) Description: These routines return address for the hardware ink layer through which the application can directly access the ink layer memory. Call seGetInkLinearAddress() to retrieve the address of the ink layer associated with the current active surface.

  • Page 380

    Page 146 Epson Research and Development Vancouver Design Center void seSetInkColor(int index, DWORD color) void seSetLcdInkColor(int index, DWORD color) void seSetCrtInkColor(int index, DWORD color) void seSetTvInkColor(int index, DWORD color) Description: These routines allow the user to set the either of the two user definable hardware ink layer colors.

  • Page 381

    Epson Research and Development Page 147 Vancouver Design Center void seDrawInkLine(long x1, long y1, long x2, long y2, DWORD color) void seDrawLcdInkLine(long x1, long y1, long x2, long y2, DWORD color) void seDrawCrtInkLine(long x1, long y1, long x2, long y2, DWORD color)

  • Page 382

    Page 148 Epson Research and Development Vancouver Design Center void seDrawInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill) void seDrawLcdInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill) void seDrawCrtInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)

  • Page 383: Pci Support

    To overcome these obstacles the standard PCI evaluation boar is PCI based. By placing the S1D13506 evaluation board on a PCI bus the issue of address space is elimi- nated. In addition 32 bit software can be written and debugged in a Microsoft Windows environment before being ported to an embedded platform.

  • Page 384: Porting Libse To A New Target Platform

    The following examples assume that you have a copy of the complete source code for the S1D13506 utilities, including the nmake makefiles, as well as a copy of the GNU Compiler v2.7-96q3a for Hitachi SH3.

  • Page 385: Building The Libse Library For Sh3 Target Example

    With nmake.exe in your path run: nmake -fmakesh3.mk 14.3.2 Building a complete application for the target example Source code for this example is available in the file 56_sh3_target.c. This file is available on the internet at www.eea.epson.com. Programming Notes and Examples S1D13506 Issue Date: 02/03/21...

  • Page 386

    Epson Research and Development Vancouver Design Center 15 Sample Code Example source code demonstrating programming the S1D13506 using the HAL library is availble on the internet at www.eea.epson.com. Also included are three header files that may make some of the structures used clearer.

  • Page 391: Cfg Configuration Program

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 392

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506CFG Configuration Program X25B-B-001-02 Issue Date: 01/03/14...

  • Page 393: Table Of Contents

    13506CFG ..........5 S1D13506 Supported Evaluation Platforms ..... . 5 Installation .

  • Page 394

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506CFG Configuration Program X25B-B-001-02 Issue Date: 01/03/14...

  • Page 395

    13506CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register values for a user defined S1D13506 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13506 utilities or any program built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration information can be saved in a variety of text file formats for use in other applications.

  • Page 396

    Vancouver Design Center Installation Create a directory for 13506cfg.exe and the S1D13506 utilities. Copy the files 13506cfg.exe and panels.def to that directory. Panels.def contains configuration infor- mation for a number of panels and must reside in the same directory as 13506cfg.exe.

  • Page 397: Cfg Configuration Tabs, General Tab

    13506CFG Configuration Tabs 13506CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13506 operation. The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT/TV”, and “Registers”.

  • Page 398

    PCI interface and the decode addresses are determined by the system BIOS during boot-up. If using the S1D13506 Evaluation Board on a PCI based platform, both Windows and the S1D13XXX device driver must be installed. For further information on the S1D13XXX device driver, see the S1D13XXX Windows 9x/NT/2000 Device Driver In- stallation Guide, document number X00A-E-003-xx.

  • Page 399: Preferences Tab

    The selections “None” and “Panel” are always available. Panel SwivelView The S1D13506 SwivelView feature is capable of rotating the image displayed on an LCD panel 90°, 180°, or 270° in a clockwise direction. This sets the initial orientation of the panel.

  • Page 400: Memory Tab

    DRAM manufacturer’s specification, unless otherwise noted. Access Time Selects the access time of the DRAM. The S1D13506 evaluation boards use 50ns DRAM. Memory Type Selects the memory type, either Extended Data Out (EDO) or Fast Page Mode (FPM).

  • Page 401

    If this option is selected, the memory contents are lost during power save. Installed Memory Selects the amount of DRAM available for the display buffer. The S1D13506 evaluation board use 2M bytes of DRAM. 13506CFG Configuration Program S1D13506 Issue Date: 01/03/14...

  • Page 402: Clocks Tab

    The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. In automatic mode the values for CLKI and CLKI2 are calculated based on selections made for LCD and CRT/TV timings from the “Panel”...

  • Page 403

    Epson Research and Development Page 13 Vancouver Design Center The S1D13506 may use as many as three input clocks or as few as one. The more clocks used the greater the flexibility of choice in display type and memory speed. CLKI This setting determines the frequency of CLKI.

  • Page 404

    Page 14 Epson Research and Development Vancouver Design Center LCD PCLK These settings select the signal source and input clock divisor for the panel pixel clock (LCD PCLK). Source Selects the LCD PCLK source. Possible sources include CLKI, CLKI2, BUSCLK or MCLK. Typically the LCD PCLK is derived from CLKI.

  • Page 405

    Epson Research and Development Page 15 Vancouver Design Center MCLK These settings select the signal source and input clock divisor for the memory clock (MCLK). MCLK should be set based on the type and speed of DRAM as follows. Optimal Memory Clock (MCLK)

  • Page 406: Panel Tab

    TFT/FPLINE Non-Display TFT/FPFRAME Period The S1D13506 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type Selects between passive (STN) and active (TFT) panel types. Select TFT for TFT compatible D-TFD panel types.

  • Page 407

    Selects color STN panel format 2. This option is specif- ically for configuring 8-bit color STN panels. See the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx, for description of format 1 / format 2 data formats. Most new panels use the format 2 data format.

  • Page 408

    TFT/FPLINE (pixels) These settings allow fine tuning of the TFT/D-TFT line pulse parameters and are only available when the selected panel type is TFT. Refer to S1D13506 Hardware Functional Specification, document number X25B-A-001-xx for a complete description of the FPLINE pulse settings.

  • Page 409

    TFT/FPFRAME (lines) These settings allow fine tuning of the TFT/D-TFT frame pulse parameters and are only available when the selected panel type is TFT. Refer to S1D13506 Hardware Functional Specification, document number X25B-A-001-xx, for a complete description of the FPFRAME pulse settings.

  • Page 410: Crt/tv Tab

    Page 20 Epson Research and Development Vancouver Design Center CRT/TV Tab Display Dimensions TV Filters Display Selection TV Output CRT DAC Output Level The CRT/TV tab configures settings specific to CRT/TV display devices. Display Selection Select the type of alternate display from: CRT, TV/NTSC, or TV/PAL.

  • Page 411

    Page 21 Vancouver Design Center TV Filters When displaying computer images on a TV, several image distortions may arise. The S1D13506 incorpo- rates three filters which reduce these distortions. Each filter type is enabled by checking the associated box. Luminance The luminance filter adjusts the brightness of the TV and reduces the “rainbow-like”...

  • Page 412: Registers Tab

    Vancouver Design Center Registers Tab The Registers tab allows viewing and direct editing the S1D13506 register values. Scroll up and down the list of registers and view their configured value. Individual register settings may be changed by double-clicking on the register in the listing. Manual changes to the registers are not checked for errors, so caution is warranted when directly editing these values.

  • Page 413: Cfg Menus

    This may be used to quickly arrive at a starting point for register configuration. The only requirement is that the file being opened must contain a valid S1D13506 HAL library information block. 13506CFG supports a variety of executable file formats. Select the file type(s) 13506CFG should display in the Files of Type drop-down list and then select the filename from the list and click on the Open button.

  • Page 414: Save As

    Page 24 Epson Research and Development Vancouver Design Center Save From the Menu Bar, select “File”, then “Save” to initiate the save action. The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option.

  • Page 415: Configure Multiple

    Epson Research and Development Page 25 Vancouver Design Center Configure Multiple After determining the desired configuration, “Configure Multiple” allows the information to be saved into one or more executable files built with the HAL library. From the Menu Bar, select “File”, then “Configure Multiple” to display the Configure Multiple Dialog Box.This dialog box is also displayed when a file(s) is dragged onto the...

  • Page 416

    “Preview” button starts Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13506 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button.

  • Page 417: Enable Tooltips, Erd On The Web, About 13506cfg

    Tooltips are enabled by default. ERD on the Web This “Help” menu item is actually a hotlink to the Epson Research and Development website. Selecting “Help” then “ERD on the Web” starts the default web browser and points it to the ERD product web site.

  • Page 418

    Page 28 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506CFG Configuration Program X25B-B-001-02 Issue Date: 01/03/14...

  • Page 419

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 420

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506SHOW Demonstration Program X25B-B-002-03 Issue Date: 01/02/06...

  • Page 421

    Vancouver Design Center 13506SHOW 13506SHOW is designed to demonstrate and test some of the S1D13506 display capabil- ities. The program can cycle through all color depths and display a pattern showing all available colors or shades of gray. Alternately, the user can specify a color depth and display configuration.

  • Page 422

    Page 4 Epson Research and Development Vancouver Design Center Usage PC Platform At the prompt, type: 13506SHOW [/a] [bl=n] [bc=n] [ds=n | ds=?] [/g] [/noinit] [/r90 | /r180 | /r270] [/read] [/s] [/write] [/?] Embedded platform Execute 13506show and type the command line argument at the prompt.

  • Page 423

    Epson Research and Development Page 5 Vancouver Design Center /read after drawing the image, continually reads from the screen (for testing purposes). displays a vertical stripe pattern. /write continually writes to one word of offscreen memory (for testing purposes only).

  • Page 424

    13506SHOW Examples 13506SHOW is designed to both demonstrate and test some of the features of the S1D13506. The following examples show how to use the program in both instances. Using 13506SHOW For Demonstration 1. To show color patterns which must be manually stepped through, type the following:...

  • Page 425

    Epson Research and Development Page 7 Vancouver Design Center 5. To show the color patterns in SwivelView™ 90° mode, type the following: 13506SHOW /r90 The program will display the default color depth (as selected in 13506CFG). Press any key to go to the next screen. Since SwivelView™ 90° is limited to color depths of 8, 15 and 16 bpp the program exits.

  • Page 426

    Page 8 Epson Research and Development Vancouver Design Center Comments • If 13506SHOW is started without defining the color depth, the program automatically cycles through the available color depths from highest to lowest. The first color depth shown is the default color depth value saved to 13506SHOW using 13506CFG. This approach avoids showing color depths not supported by a given hardware configuration.

  • Page 427

    Page 9 Vancouver Design Center Program Messages ERROR: Could not detect S1D13506. The ID register did not indicate the presence of the 13506. ERROR: Could not map memory from evaluation board to host platform. This message should only be shown for DOS platforms. In this case the DOS extender could not be initialized, or was unable to get the linear address of the display memory.

  • Page 428

    Page 10 Epson Research and Development Vancouver Design Center ERROR: Not enough memory for LCD/CRT/TV in 4/8/16 bits-per-pixel. 13506SHOW is unable to change the color depth due to insufficient display buffer memory. Memory requirements depend on: • the display resolution(s).

  • Page 429

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 430

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506PLAY Diagnostic Utility X25B-B-003-02 Issue Date: 01/02/06...

  • Page 431

    Vancouver Design Center 13506PLAY 13506PLAY is a diagnostic utility which allows the user to read/write to all the S1D13506 Registers, Look-Up Tables and Display Buffer. 13506PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms).

  • Page 432

    Page 4 Epson Research and Development Vancouver Design Center Installation PC platform Copy the file 13506play.exe to a directory in the path (e.g. PATH=C:\S1D13506). Embedded platform Download the program 13506play to the system. Usage PC platform At the prompt, type:...

  • Page 433

    Epson Research and Development Page 5 Vancouver Design Center Commands The following commands are designed to be used from within the 13506PLAY program. However, simple commands can also be executed from the command line. If a command with multiple arguments is executed from the command line, it must be enclosed in double quotes (e.g.

  • Page 434

    Number of lines that will be shown before halting the displayed data (decimal value). I [?] {LCD|CRT|TV} [d=iCrtTv] [COMP | SVIDEO] [FLICKER=ON | OFF] Initializes the S1D13506 registers for a given display type. Where: Displays a help message. Initializes the LCD registers.

  • Page 435

    Epson Research and Development Page 7 Vancouver Design Center IC {LCD|CRT|TV} Initializes the Hardware Cursor for a given display type. Where: Initializes for the LCD display. Initializes for the CRT display. Initializes for the TV display. II {LCD|CRT|TV} Initializes the Ink Layer for a given display type.

  • Page 436

    Page 8 Epson Research and Development Vancouver Design Center M [?] {LCD|CRT|TV} [bpp] Sets the color depth (bpp) for the specified display type. If no color depth is provided, infor- mation about the current setting on the specified display are listed.

  • Page 437

    Epson Research and Development Page 9 Vancouver Design Center S {CLKI | CLKI2 | BUSCLK} freq Sets PCLK source frequency (in kHz). Where: CLKI Sets PCLK source to CLKI. CLKI2 Sets PCLK source to CLKI2. BUSCLK Sets PCLK source to BUSCLK.

  • Page 438

    Page 10 Epson Research and Development Vancouver Design Center Reads all the S1D13506 registers. XD index [data] Writes dword data to the register at index. If no data is specified, reads the 32-bit (dword) data from the register at index.

  • Page 439

    Epson Research and Development Page 11 Vancouver Design Center 13506PLAY Example 1. Type 13506PLAY to start the program. 2. Type ? for help. 3. Type i LCD to initialize the registers. 4. Type xa to display the contents of the registers.

  • Page 440

    “results.” Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the S1D13506 and reads the registers. ; Note: after a semicolon (;), all characters on a line are ignored.

  • Page 441

    Epson Research and Development Page 13 Vancouver Design Center Program Messages ERROR: Could not map memory from evaluation board to host platform. This message should only be shown for DOS platforms. In this case the DOS extender could not be initialized, or was unable to get the linear address of the display memory.

  • Page 442

    Page 14 Epson Research and Development Vancouver Design Center ERROR: Not enough display buffer memory for LCD/CRT/TV cursor/ink layer. There was insufficient display buffer memory for the given Hardware Cursor/Ink Layer configu- ration. Memory requirements depend on: • the display resolution(s).

  • Page 443

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 444

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506BMP Demonstration Program X25B-B-004-02 Issue Date: 01/02/06...

  • Page 445

    Vancouver Design Center 13506BMP 13506BMP is a demonstration utility used to show the S1D13506 display capabilities by rendering bitmap images on the display device(s). The program will display any bitmap stored in Windows BMP file format and then exit. 13506BMP supports SviwelView™...

  • Page 446

    Page 4 Epson Research and Development Vancouver Design Center Usage At the prompt, type: 13506bmp bmpfile [ds=n | ds=?] [/noinit] [/r90 | /r180 | /r270] [/v] [/?] Where: bmpfile specifies filename of a windows format bmp image ds=n selects display surfaces (see Section , “Display Surfaces”...

  • Page 447

    Epson Research and Development Page 5 Vancouver Design Center Display Surfaces A surface is a block of memory assigned to one or more physical display devices. 13506BMP provides 7 display surfaces (0-6) which cover the possible combinations of display types. Table 1:, “Display Surfaces” lists the predefined display surfaces that may be selected.

  • Page 448

    Page 6 Epson Research and Development Vancouver Design Center 13506BMP Examples To display a bmp image on an LCD, type the following: 13506bmp bmpfile.bmp ds=0 To display a bmp image on a CRT, type the following: 13506bmp bmpfile.bmp ds=1 To display a bmp image on an LCD with 90° SwivelView™ enabled, type the following: 13506bmp bmpfile.bmp ds=0 /r90...

  • Page 449

    Program Messages ERROR: Could not detect S1D13506. The ID register did not indicate the presence of the S1D13506. ERROR: Could not map memory from evaluation board to host platform. This message should only be shown for DOS platforms. In this case the DOS extender could not be initialized, or was unable to get the linear address of the display memory.

  • Page 450

    Page 8 Epson Research and Development Vancouver Design Center ERROR: Not enough memory for LCD/CRT/TV in 4/8/15/16 bits-per-pixel. 13506BMP is unable to change the color depth due to insufficient display buffer memory. Memory requirements depend on: • the display resolution(s).

  • Page 451

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 452

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506FILT Test Utility X25B-B-005-02 Issue Date: 01/02/06...

  • Page 453

    13506FILT 13506FILT is an interactive Windows® 9x/NT program that enables/disables the S1D13506 TV Filters. It demonstrates the effect each filter has on a pre-loaded TV image. 13506FILT is particularly useful in a test or demonstration environment where 13506FILT is run on one display and the effects of enabling/disabling each filter are seen on a TV. An OEM may find this useful in determining the appropriate filters for their application.

  • Page 454

    Page 4 Epson Research and Development Vancouver Design Center Filter Dialog Box The filter dialog box controls which TV filters are enabled/disabled during NTSC or PAL output. The check box for each filter determines if the filter is enabled or disabled. When the box is checked the filter is enabled.

  • Page 455

    Epson Research and Development Page 5 Vancouver Design Center Filter Descriptions When displaying computer images on a TV, several image distortions are likely to arise: • flickering. • cross-chrominance distortion. • cross-luminance distortion. These distortions are caused by the high-resolution nature of computer images which typically contain sharp chrominance (color) transitions, and sharp luminance (brightness) transitions.

  • Page 456

    Manual, document number X25B-B-004-xx). • The chrominance and luminance filters are intended for use with composite output. • For information on manually enabling/disabling the TV filters, refer to the S1D13506 Hardware Functional Specification (document number X25B-A-001-xx) and the S1D13506 Programming Notes and Examples (document number X25B-G-003-xx).

  • Page 457

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 458

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 13506SWIVEL Demonstration Utility X25B-B-006-02 Issue Date: 01/02/06...

  • Page 459

    13506SWIVEL 13506SWIVEL is a command line utility that demonstrates the SwivelView™ feature of the S1D13506. The SwivelView feature provides hardware rotation of a predefined image by 90°, 180°, and 270° in a clockwise direction. 13506SWIVEL cycles through each SwivelView mode, advancing to the next mode when a key is pressed.

  • Page 460

    • 13506SWIVEL must be configured for LCD only using the utility 13506CFG. For further information on 13506CFG, refer to the 13506CFG Users Manual, document number X25B-B-001-xx. • For further information on SwivelView™, refer to the S1D13506 Hardware Functional Specification (document number X25B-A-001-xx) and the S1D13506 Programming Notes and Examples (document number X25B-G-003-xx).

  • Page 461

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 462

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Windows® CE 2.x Display Drivers X25B-E-001-06 Issue Date: 01/05/31...

  • Page 463

    Vancouver Design Center WINDOWS® CE 2.x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13506 Color LCD/CRT/TV Controller running under the Microsoft Windows CE 2.x operating system. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 4, 8 and 16 bit-per- pixel SwivelView™...

  • Page 464

    Click on “Shortcut” and replace the string “DEMO1” under the entry “Target” with “DEMO7”. Click on “OK” to finish. 5. Create a sub-directory named S1D13506 under x:\wince\platform\cepc\drivers\dis- play. 6. Copy the source code to the S1D13506 subdirectory. S1D13506 Windows® CE 2.x Display Drivers X25B-E-001-06 Issue Date: 01/05/31...

  • Page 465

    8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the de- fault display driver to the file EPSON.DLL (EPSON.DLL will be created during the build in step 13). Replace or comment out the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll...

  • Page 466

    2. Install Microsoft Visual C/C++ version 5.0 or 6.0. 3. Install Platform Builder 2.1x by running SETUP.EXE from compact disk #1. 4. Follow the steps below to create a “Build Epson for x86” shortcut which uses the current “Minshell” project icon/shortcut on the Windows desktop.

  • Page 467

    Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right clicking on the icon and choosing “rename”. g. Right click on the icon “Build Epson for x86” and click on “Properties” to bring up the “Build Epson for x86 Properties” window.

  • Page 468

    13506CFG, refer to the 13506CFG Configuration Program User Manual, document number X25B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13506 WinCE Drivers”. Save the new configuration as MODE0.H in x:\wince\platform\cepc\drivers\display\S1D13506, replacing the original configura- tion file.

  • Page 469

    12. Generate the proper building environment by double-clicking on the Epson project icon --”Build Epson for x86”. 13. Type BLDDEMO <ENTER> at the command prompt of the “Build Epson for x86” window to generate a Windows CE image file (NK.BIN).

  • Page 470

    Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.

  • Page 471

    Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13506 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.

  • Page 472

    This option is used to enable support for the ICD2061A clock generator. This clock chip is used on the S5U13506B00C evaluation board. The S1D13506 display drivers can program the clock chip to support the frequencies required in the MODE tables.

  • Page 473

    Epson Research and Development Page 13 Vancouver Design Center This option should be disabled unless the image is required for debugging. DEBUG_BLT This option enables special BLT debugging messages on the debugging serial port. This option, when enabled, will drastically impact display driver performance, and should only be used to track down failures in the BLT operations.

  • Page 474

    Clocks tab of the 13506CFG program. If you run the S1D13506 with a single clock source, make sure your clock sources for LCD, CRT, MediaPlug, and MCLK are correctly set to use the correct clock input source (typically BUSCLK).

  • Page 475

    Epson Research and Development Page 15 Vancouver Design Center • When using 13506CFG.EXE to produce multiple MODE tables, make sure you change the Mode Number in the WinCE tab for each mode table you generate. The display driver supports multiple mode tables, but only if each mode table has a unique mode number.

  • Page 476

    Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Windows® CE 2.x Display Drivers X25B-E-001-06 Issue Date: 01/05/31...

  • Page 477

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 478

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Wind River WindML v2.0 Display Drivers X25B-E-002-03 Issue Date: 01/04/06...

  • Page 479

    The source code is written for portability and contains functionality for most features of the S1D13506. Source code modification is required to provide a smaller, more efficient driver for mass production (e.g. TV support may be removed for products not requiring TV).

  • Page 480

    Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2.0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program. These instructions assume that Wind River’s Tornado platform is already installed.

  • Page 481

    Mode0.h should be created using the configuration utility 13506CFG. For more infor- mation on 13506CFG, see the 13506CFG Configuration Program User Manual, docu- ment number X25B-B-001-xx available at www.erd.epson.com. 6. Build the WindML v2.0 library. From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”...

  • Page 482

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Wind River WindML v2.0 Display Drivers X25B-E-002-03 Issue Date: 01/04/06...

  • Page 483

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 484

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Wind River UGL v1.2 Display Drivers X25B-E-003-02 Issue Date: 01/02/06...

  • Page 485

    S1D13506. Source code modification is required to provide a smaller, more efficient driver for mass production (e.g. TV support may be removed for products not requiring TV).

  • Page 486

    Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1.2 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo software. These instructions assume that the Wind River Tornado platform is correctly installed.

  • Page 487

    Mode0.h should be created using the configuration utility 13506CFG. For more infor- mation on 13506CFG, see the 13506CFG Configuration Program User Manual, docu- ment number X25B-B-001-xx available at www.erd.epson.com. 6. Open the S1D13506 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13506\8bpp\13506.wsp”...

  • Page 488

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Wind River UGL v1.2 Display Drivers X25B-E-003-02 Issue Date: 01/02/06...

  • Page 489

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 490

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 QNX Photon v2.0 Display Driver X25B-E-005-02 Issue Date: 01/09/10...

  • Page 491

    “reference” source code for OEMs developing for QNX platforms. The driver package provides support for 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13506. Source code modification is required to provide a smaller driver for mass production.

  • Page 492

    At the root of the Project source tree, type make. Note To build drivers for X86 NTO type ‘OSLIST=nto CPULIST=x86 make’. Further builds do not require all libraries to be re-built. To build only the S1D13506 display driver, change to the directory gddk_1.0/devg/S1D13506 and type make. S1D13506 QNX Photon v2.0 Display Driver...

  • Page 493

    For the remaining steps the S5U13506B00C evaluation board must be installed on the test platform. It is recommended that the driver be verified before starting QNX with the S1D13506 as the primary display. To verify the driver: 1. Copy the data file from the services/graphics/tests/bench directory to the current di- rectory.

  • Page 494

    This command starts the bench utility which will initialize the driver as the secondary display and exercise the drivers main functions. If the display appears satisfactory, restart QNX Photon and the restart will result in the S1D13506 display driver becoming the primary display device.

  • Page 495

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 496

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Windows® CE 3.x Display Drivers X25B-E-006-01 Issue Date: 01/05/18...

  • Page 497

    Vancouver Design Center WINDOWS® CE 3.x DISPLAY DRIVERS The Windows CE 3.x display driver is designed to support the S1D13506 Color LCD/CRT/TV Controller running the Microsoft Windows CE operating system, version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™...

  • Page 498

    Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for: 1. Windows CE Platform Builder 3.00 using the GUI interface. 2. Windows CE Platform Builder 3.00 using the command-line interface.

  • Page 499

    Click the Set button. Click the OK button. 7. Create a new directory S1D13506, under x:\wince300\platform\cepc\drivers\display, and copy the S1D13506 driver source code into this new directory. 8. Add the S1D13506 driver component. a. From the Platform menu, select “Insert | User Component”.

  • Page 500

    X25B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13506 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 12. From the Platform window, click on ParameterView Tab. Show the tree for MY- PLATFORM Parameters by clicking on the ‘+’...

  • Page 501

    CEPC_DDI_S1D13506=1 4. Generate the build environment by calling cepath.bat. 5. Create a new folder called S1D13506 under x:\wince300\platform\cepc\drivers\dis- play, and copy the S1D13506 driver source code into x:\wince300\platform\cepc\driv- ers\display\S1D13506. 6. Edit the file x:\wince300\platform\cepc\drivers\display\dirs and add S1D13506 into the list of directories.

  • Page 502

    X25B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13506 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 9. Edit the file PLATFORM.REG to match the screen resolution, color depth, and rota- tion information in MODE.H.

  • Page 503

    Epson Research and Development Page 9 Vancouver Design Center 10. Delete all the files in the x:\wince300\release directory and delete the file x:\wince300\platform\cepc\*.bif 11. Type BLDDEMO <ENTER> at the command prompt to generate a Windows CE image file. The file generated will be x:\wince300\release\nk.bin.

  • Page 504

    Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.

  • Page 505

    Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13506 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.

  • Page 506

    This option is used to enable support for the ICD2061A clock generator. This clock chip is used on the S5U13506B00C evaluation board. The S1D13506 display drivers can program the clock chip to support the frequencies required in the MODE tables.

  • Page 507

    Epson Research and Development Page 13 Vancouver Design Center This option should be disabled unless the image is required for debugging. DEBUG_BLT This option enables special BLT debugging messages on the debugging serial port. This option, when enabled, will drastically impact display driver performance, and should only be used to track down failures in the BLT operations.

  • Page 508

    Page 14 Epson Research and Development Vancouver Design Center Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch = 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When the display driver starts, it will read these values in the registry and attempt to match a mode table against them.

  • Page 509

    Epson Research and Development Page 15 Vancouver Design Center ers\display\S1D13506\sources. In SOURCES, there is a line which, when uncom- mented, will instruct Windows CE to use off-screen display memory (if sufficient display memory is available): CDEFINES=$(CDEFINES) -DEnablePreferVmem 3. In the file PROJECT.REG under CE 3.0, there is a key called PORepaint (search the Windows CE directories for PROJECT.REG).

  • Page 510

    Windows CE is shut down. If dis- play memory is kept powered up (set the S1D13506 in powersave mode), then the dis- play data will be maintained and this step can be skipped.

  • Page 511

    Clocks tab of the 13506CFG program. If you run the S1D13506 with a single clock source, make sure your clock sources for LCD, CRT, MediaPlug, and MCLK are correctly set to use the correct clock input source (typically BUSCLK).

  • Page 512

    Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Windows® CE 3.x Display Drivers X25B-E-006-01 Issue Date: 01/05/18...

  • Page 513: Installation Guide

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners...

  • Page 514

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32-Bit Windows Device Driver Installation Guide X00A-E-003-04 Issue Date: 01/04/17...

  • Page 515

    This manual describes the installation of the Windows 9x/ME/NT 4.0/2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards. The file S1D13XXX.VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x/ME.

  • Page 516

    Type the driver location or select BROWSE to find it. 7. Click NEXT. 8. Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card. Select this file and click OPEN. 9. Windows then shows the path to the file. Click OK.

  • Page 517

    Type the driver location or select BROWSE to find it. 5. Click NEXT. 6. Windows will open the installation file and show the option EPSON PCI Bridge Card. 7. Click FINISH. All ISA Bus Evaluation Cards 1.

  • Page 518

    8. Select OTHER DEVICES from HARDWARE TYPE and Click NEXT. 9. Click HAVE DISK. 10. Specify the location of the driver and click OK. 11. Click OK. 12. EPSON PCI Bridge Card will appear in the list. 13. Click NEXT. 14. Windows will install the driver. 15. Click FINISH.

  • Page 519

    Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards 1. Install the evaluation board in the computer and boot the computer. 2. Go to the CONTROL PANEL and select ADD NEW HARDWARE. 3. Click NEXT.

  • Page 520

    7. Specify the location of the driver files and click OK. 8. Select the file S1D13XXX.INF and click OK. 9. Click OK. 10. The EPSON PCI Bridge Card should be selected in the list window. 11. Click NEXT. 12. Click NEXT.

  • Page 521: User Manual

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.

  • Page 522

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 523: Table Of Contents

    Technical Support ........33 EPSON LCD/CRTControllers (S1D13506) ....33...

  • Page 524

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 525: List Of Tables, List Of Figures

    Table 3-3: Jumper Settings ........10 Table 4-1: S1D13506 Memory Mapping onto 4M byte PCI Address Block ... . . 11 Table 4-2: PCI Configuration Register Read Values .

  • Page 526

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 527

    The S5U13506B00C is designed as an evaluation platform for the S1D13506 Color LCD/CRT/TV Controller chip. This user manual will be updated as appropriate. Please check the Epson Research and Development Website at http://www.erd.epson.com for the latest revision of this document before beginning any development.

  • Page 528

    Epson Research and Development Vancouver Design Center 2 Features The S5U13506B00C features the following: • S1D13506 Color LCD/CRT/TV controller chip. • Headers for connecting to a 3.3V or 5V host bus interface. • 1Mx16 EDO DRAM. • Configuration options. • Adjustable positive LCD bias power supplies from +24V to +40V.

  • Page 529: Configuration Dip Switches, Installation And Configuration

    The S5U13506B00C is designed to support as many platforms as possible. The S5U13506B00C incorporates a DIP switch and several jumpers which allow both evalu- ation board and S1D13506 LCD controller settings to be configured for a specified evalu- ation platform.

  • Page 530: Configuration Jumpers

    Page 10 Epson Research and Development Vancouver Design Center The following table shows the Host Bus Interface options available. The Host Bus Interface chosen will depend on the evaluation platform to be used. Table 3-2: Host Bus Selection MD11 Host Bus Interface...

  • Page 531: Technical Description, Pci Bus Support

    • 3.3V or 5V PCI signalling. Note In a 3.3V PCI system, the S1D13506 must be powered at 3.3V by setting jumper JP1. In a 5V PCI system, the S1D13506 may be powered at either 3.3V or 5V. Although the S1D13506 does not support the PCI bus directly, the S5U13506B00C supports the PCI bus using a PCI Bridge Adapter FPGA.

  • Page 532: On-board Pci Configuration Registers, Utility Software

    Page 12 Epson Research and Development Vancouver Design Center 4.1.1 On-Board PCI Configuration Registers Read-Only Registers The PCI Bridge Adapter FPGA provides configuration registers which contain identification information required by the PCI interface. The following values are hard-wired into these registers.

  • Page 533: Non-pci Host Interface Support, Cpu Interface Pin Mapping

    3.3V or 5V (using jumper JP1) according to the host CPU signalling voltage. 4.2.1 CPU Interface Pin Mapping The functions of the S1D13506 host interface pins are mapped to each host bus interface according to the following table. Table 4-4: CPU Interface Pin Mapping...

  • Page 534: Cpu Bus Connector Pin Mapping

    The pinouts for Connector H1 are listed in the following table. Table 4-5: CPU/BUS Connector (H1) Pinout Pin No. Function Connected to DB0 of the S1D13506 Connected to DB1 of the S1D13506 Connected to DB2 of the S1D13506 Connected to DB3 of the S1D13506...

  • Page 535

    +5 volt supply, required in non-PCI applications Connected to RD/WR# of the S1D13506 Connected to BS# of the S1D13506 Connected to S1D13506 BUSCLK if JP4 is in position 2-3 Connected to RD# of the S1D13506 Connected to AB20 of the S1D13506...

  • Page 536: Lcd Support

    18-bit TFT/D-TFD panel, the S1D13506 can display 64K of a possible 256K colors because only 16 of the18 bits of LCD data are available from the S1D13506. For details, refer to the S1D13506 Hardware Functional Specification, document number X25B-A- 001-xx.

  • Page 537: Lcd Interface Pin Mapping

    AC Timing section of the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. The S5U13506B00C was designed using S1D13506 pin 75 (LCDPWR) to control the LCD bias power. This design is no longer supported. Applications should use one of the available GPIO pins to control the LCD bias power allowing for software control of power sequencing delays.

  • Page 538: Buffered Lcd Connector, Bit Passive Color Panel Support With Mediaplug Enabled

    Vancouver Design Center 4.3.2 Buffered LCD Connector J1 provides the same LCD panel signals as those directly from S1D13506, but with voltage-adapting buffers which can be set to 3.3V or 5V. Pin 32 on this connector provides power for the LCD panel logic at the same voltage as the buffer power supply.

  • Page 539: Adjustable Lcd Panel Positive Power Supply, Adjustable Lcd Panel Negative Power Supply

    The voltage on VDDH can be adjusted using R15 to provide an output voltage from +24V to +40V and can be enabled and disabled by LCDPWR (S1D13506 pin 75). The S5U13506B00C was designed using LCDPWR (pin 75) to control the LCD bias power.

  • Page 540: Crt/tv Support, Crt/tv Interface Pin Mapping, Crt Support, Tv Support

    Chrominance 4.4.2 CRT Support CRT support is provided on connector J3 via the S1D13506 embedded RAMDAC. An external current reference is implemented to provide the necessary RAMDAC output gain. The reference current (IREF) should be set to 4.6mA using jumper JP7.

  • Page 541

    TTL compatible and can be driven by the S1D13506 powered at 3.3V or 5V. Therefore, the power supply to the camera is 5V while the S1D13506 can powered at 3.3V or 5V. However, if the S1D13506 is powered at 5V, then 150nH inductors must be added at locations L8, L10, L11, L12 and L13.

  • Page 542: Clock Synthesizer And Clock Options, Clock Programming

    4.6.1 Clock Programming The S1D13506 utilities automatically program the clock generator. If manual programming of the clock generator is required, refer to the source code for the S1D13506 utilities available on the internet at www.eea.epson.com. For further information on programming the clock generator, refer to the Cypress ICD2061A specification.

  • Page 543

    5 References 5.1 Documents • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx. • Cypress Semiconductor Corporation, ICD2061A Data Sheet. 5.2 Document Sources •...

  • Page 544: Parts List

    Page 24 Epson Research and Development Vancouver Design Center 6 Parts List Table 6-1: Parts List Item Quantity Reference Part Description C1-C6,C10,C13-C16,C32-C34, 0.1uF 1206 capacitor +/-20% 50V C46-C49,C52,C54,C55,C57 C7,C8,C9,C38 0.01uF 1206 capacitor +/-20% 50V C11,C12,C40,C45,C53,C56 10uF/16V Tantalum size C, 10uF 16V +/-10%...

  • Page 545

    Epson Research and Development Page 25 Vancouver Design Center Table 6-1: Parts List (Continued) Item Quantity Reference Part Description 100K potentiometer Spectrol 63S104T607 R24,R25,R30 1206 resistor +/-5% R31,R32,R33 150 1% 1206 resistor +/-1% 6.04K 1% 1206 resistor +/-1% R35,R38,R41,R44,R48,R53 68 Ohms 1206 resistor +/-5% 1.5K 1%...

  • Page 546: Schematic Diagrams

    Page 26 Epson Research and Development Vancouver Design Center 7 Schematic Diagrams Figure 7-1: S5U13506B00C Schematic Diagram (1 of 7) S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 547

    Epson Research and Development Page 27 Vancouver Design Center Figure 7-2: S5U13506B00C Schematic Diagram (2 of 7) S5U13506B00C Evaluation Board User Manual S1D13506 Issue Date: 01/11/14 X25B-G-004-07...

  • Page 548

    Page 28 Epson Research and Development Vancouver Design Center Figure 7-3: S5U13506B00C Schematic Diagram (3 of 7) S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 549

    Epson Research and Development Page 29 Vancouver Design Center Figure 7-4: S5U13506B00C Schematic Diagram (4 of 7) S5U13506B00C Evaluation Board User Manual S1D13506 Issue Date: 01/11/14 X25B-G-004-07...

  • Page 550

    Page 30 Epson Research and Development Vancouver Design Center Figure 7-5: S5U13506B00C Schematic Diagram (5 of 7) S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 551

    Epson Research and Development Page 31 Vancouver Design Center Figure 7-6: S5U13506B00C Schematic Diagram (6 of 7) S5U13506B00C Evaluation Board User Manual S1D13506 Issue Date: 01/11/14 X25B-G-004-07...

  • Page 552

    Page 32 Epson Research and Development Vancouver Design Center Figure 7-7: S5U13506B00C Schematic Diagram (7 of 7) S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 553: Technical Support

    Epson Research and Development Page 33 Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRTControllers (S1D13506) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 554

    Page 34 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506B00C Evaluation Board User Manual X25B-G-004-07 Issue Date: 01/11/14...

  • Page 555

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 556

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the PC Card Bus X25B-G-005-03 Issue Date: 01/02/06...

  • Page 557: Table Of Contents

    Memory Access Cycles ....... . . 8 S1D13506 Host Bus Interface ......11 PC Card Host Bus Interface Pin Mapping .

  • Page 558

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the PC Card Bus X25B-G-005-03 Issue Date: 01/02/06...

  • Page 559

    Figure 2-2: PC Card Write Cycle ........10 Figure 4-1: Typical Implementation of PC Card to S1D13506 Interface ....14...

  • Page 560

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the PC Card Bus X25B-G-005-03 Issue Date: 01/02/06...

  • Page 561

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 562: The Pc Card System Bus, Pc Card Overview, Memory Access Cycles

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1...

  • Page 563

    Epson Research and Development Page 9 Vancouver Design Center During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle.

  • Page 564

    Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus. A[25:0] ADDRESS VALID REG# CE1# CE2# WAIT# Hi-Z D[15:0] Hi-Z DATA VALID Transfer Start Transfer Complete Figure 2-2: PC Card Write Cycle...

  • Page 565

    The S1D13506 implements a 16-bit PC Card (PCMCIA) Host Bus Interface which is used to interface to the PC Card bus. The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 566: Pc Card Host Bus Interface Signals

    The S1D13506 PC Card Host Bus Interface requires the following signals from the PC Card bus. • BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 567: Pc Card To S1d13506 Interface

    The S1D13506 provides a “glueless” interface to the PC Card bus except for the following. • The RESET# signal on the S1D13506 is active low and must be inverted to support the active high RESET provided by the PC Card interface.

  • Page 568

    Oscillator CLKI Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of PC Card to S1D13506 Interface...

  • Page 569

    Vancouver Design Center 4.2 S1D13506 Hardware Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 570

    Vancouver Design Center 4.4 Register/Memory Mapping The S1D13506 is a memory mapped device. The internal registers require 47 bytes and are mapped in the lower PC Card memory address space starting at zero.The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address space (ranging from 200000h to 3FFFFFh).

  • Page 571

    OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13506 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com. Interfacing to the PC Card Bus...

  • Page 572

    • PC Card (PCMCIA) Standard, March 1997 • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx.

  • Page 573

    Epson Research and Development Page 19 Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13506) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 574

    Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the PC Card Bus X25B-G-005-03 Issue Date: 01/02/06...

  • Page 575: Power Consumption

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 576

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Power Consumption X25B-G-006-02 Issue Date: 01/02/08...

  • Page 577

    • Internal CLK divide: internal registers allow the input clock to be divided before going to the internal logic blocks – the higher the divide, the lower the power consumption. There is a power save mode in the S1D13506. The power consumption is affected by various system design variables.

  • Page 578

    Page 4 Epson Research and Development Vancouver Design Center 1.1 Conditions Table 1-1: “S1D13506 Power Consumption” gives an example of a specific environment and its effects on power consumption. Table 1-1: S1D13506 Power Consumption Power Save Mode S1D13506 Test Condition...

  • Page 579

    CPU performance and LCD/CRT frame-rate, whereas power save mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13506 can be configured to be an extremely power-efficient LCD/CRT/TV Controller with high performance and flexibility.

  • Page 580

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Power Consumption X25B-G-006-02 Issue Date: 01/02/08...

  • Page 581

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation.

  • Page 582

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4102/VR4111™ Microprocessors X25B-G-007-02 Issue Date: 01/02/08...

  • Page 583

    LCD Memory Access Cycles ......9 S1D13506 Host Bus Interface ......10 Host Bus Interface Pin Mapping .

  • Page 584

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4102/VR4111™ Microprocessors X25B-G-007-02 Issue Date: 01/02/08...

  • Page 585

    Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles ......9 Figure 4-1: NEC VR4102/VR4111 to S1D13506 Configuration Schematic ....12 Interfacing to the NEC VR4102/VR4111™...

  • Page 586

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4102/VR4111™ Microprocessors X25B-G-007-02 Issue Date: 01/02/08...

  • Page 587

    Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC 4102 (µPD30102) or V 4111 (µPD30111) Microprocessors.

  • Page 588

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the VR4102/VR4111 2.1 The NEC VR4102/VR4111 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE based embedded consumer applications in mind, the VR4102/VR4111 offers a highly integrated solution for portable systems.

  • Page 589

    Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle.

  • Page 590

    MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4102/VR4111 microprocessor. The MIPS/ISA Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 591

    The S1D13506 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 592: Hardware Description

    BUSCLK RD/WR# Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V...

  • Page 593

    Vancouver Design Center 4.2 S1D13506 Hardware Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 594

    Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13506CFG, or by directly modifying the source.

  • Page 595

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 596

    Page 16 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13506) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 597

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 598

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Motorola MPC821 Microprocessor X25B-G-008-03 Issue Date: 01/02/08...

  • Page 599: Table Of Contents

    User-Programmable Machine (UPM) ......12 S1D13506 Host Bus Interface ......13 PowerPC Host Bus Interface Pin Mapping .

  • Page 600

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Motorola MPC821 Microprocessor X25B-G-008-03 Issue Date: 01/02/08...

  • Page 601

    Table 3-1: PowerPC Host Bus Interface Pin Mapping ......13 Table 4-1: List of Connections from MPC821ADS to S1D13506 ....16 Table 4-2: Summary of Power-On/Reset Options .

  • Page 602

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Motorola MPC821 Microprocessor X25B-G-008-03 Issue Date: 01/02/08...

  • Page 603

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the Motorola MPC821 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 604: Interfacing To The Mpc, The Mpc8xx System Bus, Mpc821 Bus Overview

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2.1 The MPC8xx System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.

  • Page 605: Normal (non-burst) Bus Transactions

    Epson Research and Development Page 9 Vancouver Design Center 2.2.1 Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: •...

  • Page 606: Burst Cycles

    Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: “Power PC Memory Write Cycle” on page 10 illustrates a typical memory write cycle on the Power PC system bus. SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Valid Transfer Start...

  • Page 607: Memory Controller Module, General-purpose Chip Select Module (gpcm)

    S1D13506, therefore the interfaces described in this document do not attempt to support burst cycles. However, the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13506 address space. 2.3 Memory Controller Module 2.3.1 General-Purpose Chip Select Module (GPCM)

  • Page 608: User-programmable Machine (upm)

    In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibility to accommodate the S1D13506 and it is desirable to leave the UPM free to handle other interfacing duties, such as EDO DRAM.

  • Page 609: Powerpc Host Bus Interface Pin Mapping

    The S1D13506 implements a 16-bit native PowerPC host bus interface which is used to interface to the MPC821 microprocessor. The PowerPC host bus interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 610: Powerpc Host Bus Interface Signals

    The S1D13506 PowerPC host bus interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13506 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 611: Mpc821 To S1d13506 Interface

    MPC821’s on-chip LCD controller. The S1D13506, through the use of the MPC821 chip selects, can share the system bus with all other MPC821 peripherals. The following figure demonstrates a typical implementation of the S1D13506 to MPC821 interface.

  • Page 612: Hardware Connections

    Page 16 Epson Research and Development Vancouver Design Center Table 4-1:,“List of Connections from MPC821ADS to S1D13506” on page 16 shows the connections between the pins and signals of the MPC821 and the S1D13506. Note The interface was designed using a Motorola MPC821 Application Development System (ADS).

  • Page 613

    Epson Research and Development Page 17 Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13506 (Continued) MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13506 Signal Name P12-A15 P12-C15 P12-D15 P12-A14 P12-B14 P12-D14 P12-B13 P12-C13 SRESET P9-D15...

  • Page 614

    The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the S1D13506 is addressed starting at 40 0000h. A total of 4M bytes of address space is used, where the lower 2M bytes is reserved for the S1D13506 on-chip registers and the upper 2M bytes is used to access the S1D13506 display buffer.

  • Page 615: Mpc821 Chip Select Configuration

    Chip select 4 is used to control the S1D13506. The following options are selected in the base address register (BR4): • BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13506 to 40 0000h. • AT[0:2] = 0 – ignore address type bits.

  • Page 616: Test Software

    The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map the S1D13506 to an unused 4M byte block of address space. Next, it loads the appropriate values into the option register for CS4 and writes the value 0 to the S1D13506 register REG[001h] to enable full S1D13506 memory/register decoding.

  • Page 617

    OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13506 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com. Interfacing to the Motorola MPC821 Microprocessor...

  • Page 618

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00B Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-001-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 619: Motorola Mpc821 Processor

    Epson Research and Development Page 23 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13506) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 620

    Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Motorola MPC821 Microprocessor X25B-G-008-03 Issue Date: 01/02/08...

  • Page 621

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 622

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Philips MIPS PR31500/PR31700 Processor X25B-G-009-02 Issue Date: 01/02/08...

  • Page 623: Table Of Contents

    Interfacing to the PR31500/PR31700 ......8 S1D13506 Host Bus Interface ......9 PR31500/PR31700 Host Bus Interface Pin Mapping .

  • Page 624

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Philips MIPS PR31500/PR31700 Processor X25B-G-009-02 Issue Date: 01/02/08...

  • Page 625

    Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping ....9 Table 4-1: S1D13506 Configuration for Direct Connection..... . 12 Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection .

  • Page 626

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Philips MIPS PR31500/PR31700 Processor X25B-G-009-02 Issue Date: 01/02/08...

  • Page 627

    1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13506 Color LCD/CRT Controller and the Philips MIPS PR31500/PR31700 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 628: Interfacing To The Pr31500/pr

    2 Interfacing to the PR31500/PR31700 The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this Host Bus Interface that the S1D13506 connects to the PR31500/PR31700 processor. The S1D13506 can be successfully interfaced using one of the following configurations: •...

  • Page 629: Pr31500/pr31700 Host Bus Interface Pin Mapping

    The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the PR31500/PR31700 microprocessor. The PR31500/PR31700 Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration.

  • Page 630: Pr31500/pr31700 Host Bus Interface Signals

    When the S1D13506 is configured to operate with the PR31500/PR31700, the Host Bus Interface requires the following signals: • BUSCLK is a clock input required by the S1D13506 Host Bus Interface. It is separate from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT.

  • Page 631: Direct Connection To The Philips Pr31500/pr

    Vancouver Design Center 4 Direct Connection to the Philips PR31500/PR31700 The S1D13506 was specifically designed to support the Philips MIPS PR31500/PR31700 processor. When configured, the S1D13506 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13506 occupies one PC Card slot and resides in the Attribute and IO address range.

  • Page 632

    The S1D13506 also has internal CLKI dividers providing additional flexibility. 4.2 S1D13506 Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 633

    Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the PR31500/PR31700 sees the S1D13506 on its PC Card slot as described in the table below. Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection...

  • Page 634

    5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13506 can be interfaced so as to share one of the PC Card slots. 5.1 Hardware Description...

  • Page 635

    IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13506 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Philips PR31500/PR31700” on page 11 can be used.

  • Page 636

    Vancouver Design Center 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13506CFG, or by directly modifying the source.

  • Page 637

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 638: Philips Mips Pr31500/pr31700 Processor

    Page 18 Epson Research and Development Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13506) Taiwan, R.O.C. North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.

  • Page 639

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 640

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Toshiba MIPS TX3912 Processor X25B-G-010-02 Issue Date: 01/02/08...

  • Page 641

    ....... . 8 S1D13506 Host Bus Interface ......9 TX3912 Host Bus Interface Pin Mapping .

  • Page 642

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Toshiba MIPS TX3912 Processor X25B-G-010-02 Issue Date: 01/02/08...

  • Page 643

    Table 3-1: TX3912 Host Bus Interface Pin Mapping ......9 Table 4-1: S1D13506 Configuration for Direct Connection..... . 12 Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection .

  • Page 644

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the Toshiba MIPS TX3912 Processor X25B-G-010-02 Issue Date: 01/02/08...

  • Page 645

    1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the Toshiba MIPS TX3912 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 646

    The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this Host Bus Interface that the S1D13506 connects to the TX3912 processor. The S1D13506 can be successfully interfaced using one of the following configurations: •...

  • Page 647

    The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the TX3912 microprocessor. The TX3912 Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configu- ration.

  • Page 648

    When the S1D13506 is configured to operate with the TX3912, the Host Bus Interface requires the following signals: • BUSCLK is a clock input required by the S1D13506 Host Bus Interface. It is separate from the input clock (CLKI) and should be driven by the TX3912 bus clock output DCLKOUT.

  • Page 649

    Vancouver Design Center 4 Direct Connection to the Toshiba TX3912 The S1D13506 was specifically designed to support the Toshiba MIPS TX3912 processor. When configured, the S1D13506 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13506 occupies one PC Card slot and resides in the Attribute and IO address range.

  • Page 650

    The S1D13506 also has internal CLKI dividers providing additional flexibility. 4.2 S1D13506 Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 651

    Vancouver Design Center 4.3 Memory Mapping and Aliasing The TX3912 uses a portion of the PC Card Attribute and IO space to access the S1D13506. The S1D13506 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the TX3912 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used).

  • Page 652

    5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13506 can be interfaced so as to share one of the PC Card slots. 5.1 Hardware Description...

  • Page 653

    IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13506 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Toshiba TX3912” on page 11 can be used.

  • Page 654

    Vancouver Design Center 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13506CFG, or by directly modifying the source.

  • Page 655

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 656

    Page 18 Epson Research and Development Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13506) Taiwan, R.O.C. North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.

  • Page 657

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation.

  • Page 658

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4121™ Microprocessor X25B-G-011-02 Issue Date: 01/02/08...

  • Page 659

    LCD Memory Access Cycles ......9 S1D13506 Host Bus Interface ......10 Host Bus Interface Pin Mapping .

  • Page 660

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4121™ Microprocessor X25B-G-011-02 Issue Date: 01/02/08...

  • Page 661

    Figure 2-1: NEC VR4121 Read/Write Cycles ......9 Figure 4-1: NEC VR4121 to S1D13506 Configuration Schematic ....12 Interfacing to the NEC VR4121™...

  • Page 662

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4121™ Microprocessor X25B-G-011-02 Issue Date: 01/02/08...

  • Page 663

    Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC 4121 (µPD30121) microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 664

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC V 4121 2.1 The NEC V 4121 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE based embedded consumer applications in mind, the VR4121 offers a highly integrated solution for portable systems.

  • Page 665

    Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle.

  • Page 666

    MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4121 microprocessor. The MIPS/ISA Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 667

    The S1D13506 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 668

    RD/WR# +2.5V Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V...

  • Page 669

    Vancouver Design Center 4.2 S1D13506 Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 670

    (ADD21=1) and the S1D13506 internal registers (ADD21=0). NEC V 4121 address lines ADD[23:22] are ignored, thus the S1D13506 is aliased four times at 4M byte intervals over the LCD controller address range. Address lines ADD[25:24] are set at 10b and never change while the LCD controller is being addressed.

  • Page 671

    Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13506CFG, or by directly modifying the source.

  • Page 672

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 673

    Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13506) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 674

    Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC VR4121™ Microprocessor X25B-G-011-02 Issue Date: 01/02/08...

  • Page 675

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation.

  • Page 676

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC V832™ Microprocessor X25B-G-012-03 Issue Date: 01/02/08...

  • Page 677

    ....11 V832 to S1D13506 Interface ......12 Hardware Description .

  • Page 678

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC V832™ Microprocessor X25B-G-012-03 Issue Date: 01/02/08...

  • Page 679

    Figure 2-1: NEC V832 Read/Write Cycles ....... 9 Figure 4-1: NEC V832 to S1D13506 Configuration Schematic ....12 Interfacing to the NEC V832™...

  • Page 680

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the NEC V832™ Microprocessor X25B-G-012-03 Issue Date: 01/02/08...

  • Page 681

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC V832 microprocessor (µPD705102). The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 682

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC V832 2.1 The NEC V832 System Bus This section provides an overview of the operation of the CPU bus in order to establish interface requirements. 2.1.1 Overview The NEC V832 is designed around the RISC architecture developed by MIPS.

  • Page 683

    (CSn) is driven low. The read or write enable signals (IORD or IOWR) are driven low and READY is driven low by the S1D13506 to insert wait states into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.

  • Page 684

    PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the V832 microprocessor. The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 685

    3.2 Host Bus Interface Signal Descriptions The S1D13506 PC Card Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is driven by the V832 signal SDCLKOUT.

  • Page 686

    +2.5V VDD_I Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V832 to S1D13506 Configuration Schematic Note For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,”...

  • Page 687

    Vancouver Design Center 4.2 S1D13506 Hardware Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 688

    The NEC V832 should access the S1D13506 in non-burst mode only. This is ensured by using any one of the CS3 to CS6 lines to control the S1D13506 and setting that line to respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is used then bit 5 (CT5) of the BCTC register should be set to 1 (IO cycle).

  • Page 689

    Page 15 Vancouver Design Center 4.4 Memory Mapping and Aliasing The CSn line selected determines the address range to be reserved for the S1D13506. The table below summarizes the S1D13506 address mapping. Table 4-3: NEC 832 IO Address Range For Each CSn Line...

  • Page 690

    13506CFG, or by directly modifying the source. The Windows CE display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13506 test utilities and Windows CE display drivers are available from your sales support contact or www.eea.epson.com. S1D13506 Interfacing to the NEC V832™...

  • Page 691

    • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx.

  • Page 692

    Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13506) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 693

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 694

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the StrongARM SA-1110 Processor X25B-G-013-03 Issue Date: 01/02/08...

  • Page 695

    Variable-Latency IO Access Cycles ......9 S1D13506 Host Bus Interface ......11 Host Bus Interface Pin Mapping .

  • Page 696

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the StrongARM SA-1110 Processor X25B-G-013-03 Issue Date: 01/02/08...

  • Page 697

    Figure 2-2: SA-1110 Variable-Latency IO Write Cycle ......10 Figure 4-1: Typical Implementation of SA-1110 to S1D13506 Interface ....13...

  • Page 698

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the StrongARM SA-1110 Processor X25B-G-013-03 Issue Date: 01/02/08...

  • Page 699

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the Intel StrongARM SA-1110. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 700

    The StrongARM SA-1110 microprocessor is a highly integrated communications micro- controller that incorporates a 32-bit StrongARM RISC processor core. The SA-1110 is ideally suited to interface to the S1D13506 LCD controller and provides a high perfor- mance, power efficient solution for embedded systems.

  • Page 701

    Epson Research and Development Page 9 Vancouver Design Center 2.1.3 Variable-Latency IO Access Cycles The first nOE assertion occurs two memory cycles after the assertion of chip select (nCS3, nCS4, or nCS5). Two memory cycles prior to the end of minimum nOE or nWE assertion (RDF+1 memory cycles), the SA-1110 starts sampling the data ready input (RDY).

  • Page 702

    Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus. A[25:0] ADDRESS VALID nCS4 D[31:0] DATA VALID nCAS[3:0] Figure 2-2: SA-1110 Variable-Latency IO Write Cycle S1D13506 Interfacing to the StrongARM SA-1110 Processor...

  • Page 703

    PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the SA-1110. The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 704

    The S1D13506 PC Card Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is driven by one of the SA-1110 signals SDCLK1 or SDCLK2 (the example implementa- tion in this document uses SDCLK2).

  • Page 705

    4 StrongARM SA-1110 to S1D13506 Interface 4.1 Hardware Description The S1D13506 is designed to directly support a variety of CPUs, providing an interface to each processor’s unique “local bus”. Using the S1D13506’s PC Card Host Bus Interface provides a “glueless” interface to the SA-1110.

  • Page 706

    Vancouver Design Center 4.2 S1D13506 Hardware Configuration The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.

  • Page 707

    The S1D13506 is a memory mapped device. The SA-1110 will use the memory assigned to a chip select (nCS4 in this example) to map the S1D13506 internal registers and display buffer. The internal registers require 2M bytes of memory and are mapped to the lower memory address space starting at zero.

  • Page 708

    Parameter RDNx<4:0> should be set to 0 (minimum command precharge time). Parameter RRRx<2:0> should be set to 0 (minimum nCSx precharge time). • The S1D13506 endian mode is set to little endian. To program the SA-1110 for little endian as well use the control register (register 1).

  • Page 709

    OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13506 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com. Interfacing to the StrongARM SA-1110 Processor...

  • Page 710

    Manual, Order Number 278240-001. • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx. • Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X25B-G-004-xx.

  • Page 711

    Epson Research and Development Page 19 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13506) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 712

    Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Interfacing to the StrongARM SA-1110 Processor X25B-G-013-03 Issue Date: 01/02/08...

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