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Epson S1D13506 Technical Manual

Color lcd/crt/tv controller
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Table of Contents
S1D13506 Color LCD/CRT/TV Controller
S1D13506
TECHNICAL MANUAL
Document Number: X25B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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  • Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...
  • Page 3: Riesstrasse

    Epson Research and Development Page 3 Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical manuals • Evaluation/Demonstration board manual Evaluation/Demonstration Board •...
  • Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 TECHNICAL MANUAL X25B-Q-001-06 Issue Date: 01/04/18...
  • Page 5 S1D13506 COLOR LCD/CRT/TV CONTROLLER March 2001 The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
  • Page 6 Copyright ©1998, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document.
  • Page 7: Hardware Functional Specification

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
  • Page 8 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 9: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........17 Scope .
  • Page 10 Registers ........124 Initializing the S1D13506 ......124 8.1.1...
  • Page 11: Issue Date: 02/03/26 Page

    Epson Research and Development Page 5 Vancouver Design Center 8.3.2 General IO Pins Registers ....... 126 8.3.3...
  • Page 12 15.4.3 Limitations ........208 16 EPSON Independent Simultaneous Display (EISD) ....209 16.1 Introduction .
  • Page 13 Epson Research and Development Page 7 Vancouver Design Center 19.1 Display Modes ......221 19.2 Power Save Mode .
  • Page 14 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 15 Epson Research and Development Page 9 Vancouver Design Center List of Tables Table 5-1: Host Bus Interface Pin Descriptions ......29 Table 5-2: Memory Interface Pin Descriptions .
  • Page 16 Page 10 Epson Research and Development Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing..... . . 83 Table 7-23: Single Monochrome 8-Bit Panel A.C.
  • Page 17 Table 10-1: S1D13506 Addressing ........181...
  • Page 18 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 19 Figure 3-10: Typical System Diagram (Toshiba MIPS TX3912 Bus) ....26 Figure 4-1: S1D13506 Block Diagram ....... . . 27 Figure 5-1: Pinout Diagram .
  • Page 20 Page 14 Epson Research and Development Vancouver Design Center Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing ..... . .85 Figure 7-26: Single Color 4-Bit Panel Timing .
  • Page 21 Epson Research and Development Page 15 Vancouver Design Center Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL ..195 Figure 14-1: Ink/Cursor Data Format ....... . . 197 Figure 14-2: Unclipped Cursor Positioning .
  • Page 22 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 23: Introduction

    1.2 Overview Description The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices. The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
  • Page 24: Features

    • The complete 2M byte display buffer address space is directly and contiguously avail- able through the 21-bit address bus. 2.2 CPU Interface • Supports the following interfaces: • Epson E0C33 (16-bit interface to 32-bit microprocessor). • Hitachi SH-4 bus interface. • Hitachi SH-3 bus interface. • MIPS/ISA.
  • Page 25: Display Support

    2.5 Display Features • SwivelView™: 90°, 180°, 270° hardware rotation of display image. • EPSON Independent Simultaneous Display (EISD): displays independent images on different displays (CRT or TV and passive or TFT/D-TFD panel). • Virtual Display Support: displays images larger than the panel size through the use of panning and scrolling.
  • Page 26: Clock Source

    Page 20 Epson Research and Development Vancouver Design Center 2.6 Clock Source • Memory clock can be derived from CLKI or BUSCLK pin. It can be internally divided by 2. • Pixel clock can be derived from CLKI, CLKI2, or BUSCLK pin. It can be internally divided by 2, 3 or 4.
  • Page 27: Typical System Implementation Diagrams

    Epson Research and Development Page 21 Vancouver Design Center 3 Typical System Implementation Diagrams For the pin mapping of each system implementation, see Table 5-7:, “CPU Interface Pin Mapping,” on page 40. Oscillator Oscillator Generic 4-bit FPDAT[7:4] L[3:0] Single FPSHIFT...
  • Page 28: Figure 3-2: Typical System Diagram (Hitachi Sh-4 Bus)

    Page 22 Epson Research and Development Vancouver Design Center Oscillator Oscillator SH-4 4-bit FPDAT[7:4] D[3:0] A[21] M/R# Single FPSHIFT FPSHIFT CSn# A[20:1] AB[20:1] Display FPFRAME FPFRAME D[15:0] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# WE1# S1D13506 RD/WR# GPIOx RD/WR# RED,GREEN,BLUE...
  • Page 29: Figure 3-4: Typical System Diagram (Mc68K Bus 1, Motorola 16-Bit 68000)

    Epson Research and Development Page 23 Vancouver Design Center Oscillator Oscillator MC68000 WE0# FPDAT[7:4] UD[3:0] 8-bit FPDAT[3:0] LD[3:0] A[23:21] M/R# Decoder Dual FC0, FC1 FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506...
  • Page 30: Figure 3-6: Typical System Diagram (Motorola Powerpc Bus)

    Page 24 Epson Research and Development Vancouver Design Center Oscillator Oscillator PowerPC A[0:10] M/R# Decoder 16-bit FPDAT[15:0] D[15:0] Single Decoder FPSHIFT FPSHIFT A[11:31] AB[20:0] FPFRAME FPFRAME Display D[0:15] DB[15:0] FPLINE FPLINE DRDY DRDY (MOD) WE1# S1D13506 RD/WR# GPIOx RD/WR# TSIZ0...
  • Page 31: Figure 3-8: Typical System Diagram (Pc Card Bus)

    Epson Research and Development Page 25 Vancouver Design Center Oscillator Oscillator PC Card FPDAT[15:8] UD[7:0] 16-bit FPDAT[7:0] LD[7:0] Decoder M/R# A[25:21] Dual FPSHIFT FPSHIFT Decoder FPFRAME FPFRAME Display A[20:1] AB[20:1] FPLINE FPLINE D[15:0] DB[15:0] DRDY DRDY (MOD) S1D13506 WE0# CE2#...
  • Page 32: Figure 3-10: Typical System Diagram (Toshiba Mips Tx3912 Bus)

    Page 26 Epson Research and Development Vancouver Design Center Oscillator Oscillator TX3912 M/R# FPDAT[11:0] D[11:0] 12-bit AB[16:13] FPSHIFT FPSHIFT A[12:0] AB[12:0] D[23:16] DB[15:8] FPFRAME FPFRAME Display D[31:24] DB[7:0] AB20 FPLINE FPLINE CARDREG* AB19 DRDY DRDY (MOD) S1D13506 CARDIORD* AB18 CARDIOWR*...
  • Page 33: Internal Description

    Page 27 Vancouver Design Center 4 Internal Description 4.1 Block Diagram Showing Pipelines DRAM MediaPlug Camera Memory Controller Host Pipeline CRT/TV CRT/TV Pipeline Register Encoder Power Save Figure 4-1: S1D13506 Block Diagram Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 34: Pins

    Page 28 Epson Research and Development Vancouver Design Center 5 Pins 5.1 Pinout Diagram 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...
  • Page 35: Pin Description

    Epson Research and Development Page 29 Vancouver Design Center 5.2 Pin Description Key: Input Output Bi-Directional (Input/Output) Analog Power pin CMOS level input CMOS level input with pull down resistor (typical values of 50Ω/90ΚΩ at 5V/3.3V respectively) CMOS level Schmitt input...
  • Page 36 Page 30 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State • For Philips PR31500/31700 Bus, these pins are connected to V • For Toshiba TX3912 Bus, these pins are connected to V •...
  • Page 37 • For all other busses, this input pin is used to select between the M/R# Hi-Z display buffer and register address spaces of the S1D13506. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping.
  • Page 38 This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13506 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#).
  • Page 39 Epson Research and Development Page 33 Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).
  • Page 40 Page 34 Epson Research and Development Vancouver Design Center Table 5-1: Host Bus Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see “Summary of Configuration Options”.
  • Page 41: Memory Interface

    Epson Research and Development Page 35 Vancouver Design Center 5.2.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State • For dual-CAS# DRAM, this is the column address strobe for the lower byte (LCAS#).
  • Page 42 Page 36 Epson Research and Development Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) RESET# Pin Name Type Pin # Cell Description State 58, 60, 62, Multiplexed memory address - see Memory Interface Timing on page MA[8:0] 64, 66, 67, 70 for detailed functionality.
  • Page 43: Lcd Interface

    Epson Research and Development Page 37 Vancouver Design Center 5.2.3 LCD Interface Table 5-3: LCD Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State Panel data bus. Not all pins are used for some panels - see Table 5-9:, “LCD Interface Pin Mapping,”...
  • Page 44: Crt Interface

    Page 38 Epson Research and Development Vancouver Design Center 5.2.4 CRT Interface Table 5-4: CRT Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description State HRTC Horizontal retrace signal for CRT VRTC Vertical retrace signal for CRT no output...
  • Page 45: Summary Of Configuration Options

    Epson Research and Development Page 39 Vancouver Design Center 5.3 Summary of Configuration Options Table 5-6: Summary of Power-On/Reset Options Pin Name value of this pin at rising edge of RESET# is used to configure:(1/0) Not used, value of this pin at rising edge of RESET# can be read at REG[00Ch] bit 0...
  • Page 46: Multiple Function Pin Mapping

    Note AB0 is not used internally for these busses and must be connected to either V For further information on interfacing the S1D13506 to the PC Card bus, see Interfac- ing to the PC Card Bus, document number X25B-G-005-xx. S1D13506...
  • Page 47: Table 5-8: Memory Interface Pin Mapping

    Epson Research and Development Page 41 Vancouver Design Center Table 5-8: Memory Interface Pin Mapping FPM/EDO-DRAM S1D13506 Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 Pin Names 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# MD[15:0] D[15:0] MA[8:0] A[8:0] GPIO3...
  • Page 48: Table 5-9: Lcd Interface Pin Mapping

    Page 42 Epson Research and Development Vancouver Design Center Table 5-9: LCD Interface Pin Mapping Monochrome Passive Color Passive Panel Panel S1D13506 Color TFT/D-TFD Panel Single Single Single Dual Single Single Dual Names Format 1 Format 2 4-bit 8-bit 8-bit...
  • Page 49: Table 5-10: Ma11, Ma10, Ma9, And Drdy Pin Mapping

    Epson Research and Development Page 43 Vancouver Design Center Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping MD14, MD7, MD6 MA11 MA10 DRDY GPIO2 GPIO1 GPIO3 DRDY GPIO2 GPIO1 DRDY GPIO2 GPIO1 DRDY MA11 MA10 DRDY VMPEPWR GPIO1 GPIO3...
  • Page 50: Crt/Tv Interface

    Page 44 Epson Research and Development Vancouver Design Center 5.5 CRT/TV Interface The following figure shows external circuitry for the CRT/TV interface. CRT/TV CRT Only CRT Only (REG[05Bh] bit 3 = 0) (REG[05Bh] bit 3 =1) (REG[05Bh] bit 3 =1) DAC V = 3.3V...
  • Page 51: C. Characteristics

    Epson Research and Development Page 45 Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Supply Voltage - 0.3 to 6.0 DAC V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to V + 0.5...
  • Page 52: Table 6-4: Electrical Characteristics For Vdd = 3.3V Typical

    Page 46 Epson Research and Development Vancouver Design Center Table 6-4: Electrical Characteristics for VDD = 3.3V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -2mA (Type1), High Level Output Voltage - 0.3...
  • Page 53: Table 6-5: Electrical Characteristics For Vdd = 3.0V Typical

    Epson Research and Development Page 47 Vancouver Design Center Table 6-5: Electrical Characteristics for VDD = 3.0V typical Symbol Parameter Condition Units Quiescent Current Quiescent Conditions µA Input Leakage Current µA Output Leakage Current VDD = min -1.8mA (Type1), High Level Output Voltage - 0.3...
  • Page 54: C. Characteristics

    Page 48 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: = 3.0V ± 10% and V = 5.0V ± 10% = -40° C to 85° C and T for all inputs must be < 5 ns (10% ~ 90%)
  • Page 55: Table 7-1: Generic Timing

    Epson Research and Development Page 49 Vancouver Design Center Table 7-1: Generic Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,...
  • Page 56: Hitachi Sh-4 Interface Timing

    (BUSCLK input is not divided). Note The SH-4 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. The SH-4 read-to-write idle cycle transition must be set to a non-zero value (with reference to BUSCLK).
  • Page 57: Table 7-2: Hitachi Sh-4 Timing

    Epson Research and Development Page 51 Vancouver Design Center Table 7-2: Hitachi SH-4 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...
  • Page 58: Hitachi Sh-3 Interface Timing

    BUSCLK cannot be divided by 2 in SH-3 interface mode. MD12 must be set to 0 (BUSCLK input is not divided). Note The SH-3 Wait State Control Register for the area in which the S1D13506 resides must be set to a non-zero value. S1D13506...
  • Page 59: Table 7-3: Hitachi Sh-3 Timing

    Epson Research and Development Page 53 Vancouver Design Center Table 7-3: Hitachi SH-3 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CKIO Clock period CKIO CKIO CKIO Clock pulse width low Clock pulse width high A[20:1], M/R#, RD/WR# setup to CKIO...
  • Page 60: Mips/Isa Interface Timing (E.g. Nec Vr41Xx)

    Page 54 Epson Research and Development Vancouver Design Center 7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) BUSCLK BUSCLK LatchA20 SA[19:0] M/R#, SBHE# MEMR# MEMW# IOCHRDY SD[15:0](write) SD[15:0](read) Figure 7-4: MIPS/ISA Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 61: Table 7-4: Mips/Isa Timing

    Epson Research and Development Page 55 Vancouver Design Center Table 7-4: MIPS/ISA Timing 3.0V 5.0V Symbol Parameter Units Clock frequency BUSCLK Clock period BUSCLK BUSCLK BUSCLK Clock pulse width high Clock pulse width low LatchA20, SA[19:0], M/R#, SBHE# setup to first...
  • Page 62: Motorola Mc68K Bus 1 Interface Timing (E.g. Mc68000)

    Page 56 Epson Research and Development Vancouver Design Center 7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) A[20:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) Figure 7-5: Motorola MC68000 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 63: Table 7-5: Motorola Mc68000 Timing

    Epson Research and Development Page 57 Vancouver Design Center Table 7-5: Motorola MC68000 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and...
  • Page 64: Motorola Mc68K Bus 2 Interface Timing (E.g. Mc68030)

    Page 58 Epson Research and Development Vancouver Design Center 7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) A[20:0] SIZ[1:0] M/R# R/W# DSACK1# D[31:16](write) D[31:16](read) Figure 7-6: Motorola MC68030 Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 65: Table 7-6: Motorola Mc68030 Timing

    Epson Research and Development Page 59 Vancouver Design Center Table 7-6: Motorola MC68030 Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0,...
  • Page 66: Motorola Powerpc Interface Timing (E.g. Mpc8Xx, Mc68040, Coldfire)

    Page 60 Epson Research and Development Vancouver Design Center 7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) CLKOUT CLKOUT A[11:31], RD/WR# TSIZ[0:1], M/R# t15 t16 D[0:15](write) D[0:15](read) Figure 7-7: Motorola PowerPC Timing Note BUSCLK cannot be divided by 2 in PowerPC interface mode. MD12 must be set to 0 (BUSCLK input is not divided).
  • Page 67: Table 7-7: Motorola Powerpc Timing

    Epson Research and Development Page 61 Vancouver Design Center Table 7-7: Motorola PowerPC Timing 3.0V 5.0V Symbol Parameter Units Clock frequency CLKOUT Clock period CLKOUT CLKOUT CLKOUT Clock pulse width low Clock pulse width high AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup...
  • Page 68: Pc Card Timing (E.g. Strongarm)

    Page 62 Epson Research and Development Vancouver Design Center 7.1.8 PC Card Timing (e.g. StrongARM) (provided externally) A[20:1] M/R# CE1#, CE2# WAIT# D[15:0](write) D[15:0](read) Figure 7-8: PC Card Timing Note The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
  • Page 69: Table 7-8: Pc Card Timing

    Epson Research and Development Page 63 Vancouver Design Center Table 7-8: PC Card Timing 3.0V 5.0V Symbol Parameter Units Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either...
  • Page 70: Philips Interface Timing (E.g. Pr31500/Pr31700)

    Page 64 Epson Research and Development Vancouver Design Center 7.1.9 Philips Interface Timing (e.g. PR31500/PR31700) DCLKOUT DCLKOUT ADDR[12:0] /CARDREG /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD /CARDxWAIT D[31:16](write) D[31:16](read) Figure 7-9: Philips Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 71: Table 7-9: Philips Timing

    Epson Research and Development Page 65 Vancouver Design Center Table 7-9: Philips Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...
  • Page 72: Toshiba Interface Timing (E.g. Tx39Xx)

    Page 66 Epson Research and Development Vancouver Design Center 7.1.10 Toshiba Interface Timing (e.g. TX39xx) DCLKOUT DCLKOUT ADDR[12:0] CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) Figure 7-10: Toshiba Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 73: Table 7-10: Toshiba Timing

    Epson Research and Development Page 67 Vancouver Design Center Table 7-10: Toshiba Timing 3.0V 5.0V Symbol Parameter Units Clock frequency DCLKOUT Clock period DCLKOUT DCLKOUT DCLKOUT Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle...
  • Page 74: Clock Timing

    Page 68 Epson Research and Development Vancouver Design Center 7.2 Clock Timing 7.2.1 Input Clocks V IL Figure 7-11: CLKI Clock Input Requirements Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally Symbol Parameter Units Input Clock Frequency Input Clock Period...
  • Page 75: Internal Clocks

    Epson Research and Development Page 69 Vancouver Design Center 7.2.2 Internal Clocks Table 7-13: Internal Clock Requirements Symbol Parameter Units Memory Clock Frequency MCLK LCD Pixel Clock Frequency LCD PCLK CRT/TV Pixel Clock Frequency Note 1 CRT/TV PCLK MediaPlug Clock Frequency MediaPlug Clock 1.
  • Page 76: Memory Interface Timing

    Page 70 Epson Research and Development Vancouver Design Center 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE# (read) MD (read) WE#(write) t20 t21 MD(write) Figure 7-12: EDO-DRAM Page Mode Timing...
  • Page 77: Table 7-14: Edo-Dram Read, Write, Read-Write Timing

    Epson Research and Development Page 71 Vancouver Design Center Table 7-14: EDO-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
  • Page 78: Edo-Dram Cas Before Ras Refresh Timing

    Page 72 Epson Research and Development Vancouver Design Center 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-14: EDO-DRAM CAS Before RAS Refresh Timing Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock period...
  • Page 79: Edo-Dram Self-Refresh Timing

    Epson Research and Development Page 73 Vancouver Design Center 7.3.3 EDO-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-15: EDO - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
  • Page 80: Fpm-Dram Read, Write, Read-Write Timing

    Page 74 Epson Research and Development Vancouver Design Center 7.3.4 FPM-DRAM Read, Write, Read-Write Timing Memory Clock RAS# CAS# t11 t10 t11 WE#(read) MD(read) WE#(write) t18 t19 MD(write) Figure 7-16: FPM-DRAM Page Mode Timing Memory Clock RAS# CAS# t10 t11...
  • Page 81: Table 7-17: Fpm-Dram Read, Write, Read-Write Timing

    Epson Research and Development Page 75 Vancouver Design Center Table 7-17: FPM-DRAM Read, Write, Read-Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[02Bh] bits 1-0 = 00) 5 t1 Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
  • Page 82: Fpm-Dram Cas Before Ras Refresh Timing

    Page 76 Epson Research and Development Vancouver Design Center 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-18: FPM-DRAM CAS Before RAS Refresh Timing Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock RAS# precharge time (REG[02Ah] bits 1-0 = 00) 2.45 t1...
  • Page 83: Fpm-Dram Self-Refresh Timing

    Epson Research and Development Page 77 Vancouver Design Center 7.3.6 FPM-DRAM Self-Refresh Timing MCLK can be stopped (See Note) Memory Clock RAS# CAS# Figure 7-19: FPM - DRAM Self-Refresh Timing Note MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
  • Page 84: Power Sequencing

    Page 78 Epson Research and Development Vancouver Design Center 7.4 Power Sequencing 7.4.1 LCD Power Sequencing #RESET LCD Enable Bit (REG[1FCh] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Figure 7-20: LCD Panel Power-off/Power-on Timing...
  • Page 85: Power Save Mode

    Epson Research and Development Page 79 Vancouver Design Center 7.4.2 Power Save Mode Power Save Mode Enable Bit (REG[1F0h] bit 0) FPFRAME FPLINE, FPSHIFT FPDATA, DRDY LCD Power Save Status Bit (REG[1F1h] bit 1) Memory Controller Power Save Status Bit...
  • Page 86: Table 7-21: Power Save Mode Timing

    Page 80 Epson Research and Development Vancouver Design Center Table 7-21: Power Save Mode Timing Symbol Parameter Units FPFRAME Power Save Mode Enable Bit high to FPFRAME inactive FPLINE Power Save Mode Enable Bit low to FPFRAME active FPLINE Power Save Mode Enable Bit high to FPLINE, FPSHIFT, FPDATA,...
  • Page 87: Display Interface

    Epson Research and Development Page 81 Vancouver Design Center 7.5 Display Interface 7.5.1 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPDAT[7:4] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-317 1-318...
  • Page 88: Figure 7-23: Single Monochrome 4-Bit Panel A.c. Timing

    Page 82 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-23: Single Monochrome 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 89: Table 7-22: Single Monochrome 4-Bit Panel A.c. Timing

    Epson Research and Development Page 83 Vancouver Design Center Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 90: Single Monochrome 8-Bit Panel Timing

    Page 84 Epson Research and Development Vancouver Design Center 7.5.2 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 1-633 FPDAT6 1-10 1-634 FPDAT5...
  • Page 91: Figure 7-25: Single Monochrome 8-Bit Panel A.c. Timing

    Epson Research and Development Page 85 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 92: Table 7-23: Single Monochrome 8-Bit Panel A.c. Timing

    Page 86 Epson Research and Development Vancouver Design Center Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 93: Single Color 4-Bit Panel Timing

    Epson Research and Development Page 87 Vancouver Design Center 7.5.3 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 FPDAT[7:4] LINE479 LINE480 LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-G2 1-B3 1-B319 FPDAT7 1-R320...
  • Page 94: Figure 7-27: Single Color 4-Bit Panel A.c. Timing

    Page 88 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 7-27: Single Color 4-Bit Panel A.C. Timing S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 95: Table 7-24: Single Color 4-Bit Panel A.c. Timing

    Epson Research and Development Page 89 Vancouver Design Center Table 7-24: Single Color 4-Bit Panel A.C. Timing Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 96: Single Color 8-Bit Panel Timing (Format 1)

    Page 90 Epson Research and Development Vancouver Design Center 7.5.4 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT FPSHIFT2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12...
  • Page 97: Figure 7-29: Single Color 8-Bit Panel A.c. Timing (Format 1)

    Epson Research and Development Page 91 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 FPDAT[7:0] Figure 7-29: Single Color 8-Bit Panel A.C. Timing (Format 1) Hardware Functional Specification S1D13506 Issue Date: 02/03/26 X25B-A-001-12...
  • Page 98: Table 7-25: Single Color 8-Bit Panel A.c. Timing (Format 1)

    Page 92 Epson Research and Development Vancouver Design Center Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 99: Single Color 8-Bit Panel Timing (Format 2)

    Epson Research and Development Page 93 Vancouver Design Center 7.5.5 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE DRDY (MOD) LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPDAT[7:0] FPLINE DRDY (MOD) HNDP FPSHIFT 1-R1 1-B3 1-G6 1-G638...
  • Page 100: Figure 7-31: Single Color 8-Bit Panel A.c. Timing (Format 2)

    Page 94 Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 2) S1D13506 Hardware Functional Specification X25B-A-001-12 Issue Date: 02/03/26...
  • Page 101: Table 7-26: Single Color 8-Bit Panel A.c. Timing (Format 2)

    Epson Research and Development Page 95 Vancouver Design Center Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2) Min. Max. Symbol Parameter Typical Units Setting Setting FPFRAME setup to FPLINE falling edge note 2 1268 Ts (note 1) FPFRAME hold from FPLINE falling edge...
  • Page 102: Single Color 16-Bit Panel Timing

    Page 96 Epson Research and Development Vancouver Design Center 7.5.6 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE FPDAT[15:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE HNDP FPSHIFT Invalid 1-G6 1-B11 1-G635 1-R1 Invalid FP