Lcd Interface Pin Mapping - Epson S1D13506 Technical Manual

Epson Research and Development
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4.3.1 LCD Interface Pin Mapping

S1D13506 Connector
Pin Names Pin No.
FPDAT0 1
FPDAT1 3
FPDAT2 5
FPDAT3 7
FPDAT4 9
FPDAT5 11
FPDAT6 13
FPDAT7 15
FPDAT8 17
FPDAT9 19
FPDAT10 21
FPDAT11 23
FPDAT12 25
FPDAT13 27
FPDAT14 29
FPDAT15 31
FPSHIFT 33
DRDY 35 and 38
FPLINE 37
FPFRAME 39
2-26
GND
(Even Pins)
N/C 28
VLCD 30
LCDVCC 32
+12V 34
VDDH 36
2
NC (pin 75) 40
= Driven low
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/11/14
Table 4-7: LCD Signal Connector (J1)
Monochrome Passive
Panels
Single Dual Single
4-bit 8-bit 8-bit 4-bit
D0 LD0
D1 LD1
D2 LD2
D3 LD3
D0 D4 UD0
D1 D5 UD1
D2 D6 UD2
D3 D7 UD3
MOD
Note
1
For FPDATxx to LCD interface hardware connections refer to the Display Interface
AC Timing section of the S1D13506 Hardware Functional Specification, document
number X25B-A-001-xx.
2
The S5U13506B00C was designed using S1D13506 pin 75 (LCDPWR) to control the
LCD bias power. This design is no longer supported. Applications should use one of
the available GPIO pins to control the LCD bias power allowing for software control
of power sequencing delays. For further information on LCD power sequencing, see
the S1D13506 Programming Notes and Examples, document number X25B-G-003-
xx.
Color Passive Panels
Single Single
Single
Format 1 Format 2
8-bit 8-bit 16-Bit
D0 D0
D1 D1
D2 D2
D3 D3
D0 D4 D4
D1 D5 D5
D2 D6 D6
D3 D7 D7
FPSHIFT
FPSHIFT2
FPLINE
FPFRAME
GND
N/C
Adjustable -23 to -14V negative LCD bias
+5V or +3.3V according to JP2
+12V
Adjustable +24 to +40V positive LCD bias
Panel Enable, active low (LCDPWR)
Color TFT/D-TFD
Dual
8-bit 16-bit 9-bit
D0 LD0 LD0 R2
D1 LD1 LD1 R1
D2 LD2 LD2 R0
D3 LD3 LD3 G2
D8 UD0 UD0 G1
D9 UD1 UD1 G0
D10 UD2 UD2 B2
D11 UD3 UD3 B1
D4 LD4 B0
D5 LD5
D6 LD6
D7 LD7
D12 UD4
D13 UD5
D14 UD6
D15 UD7
MOD
2
Page 17
Panels
12-bit 18-bit
R3 R5
R2 R4
R1 R3
G3 G5
G2 G4
G1 G3
B3 B5
B2 B4
B1 B3
R0 R2
R1
G0 G2
G1
G0
B0 B2
B1
DRDY
S1D13506
X25B-G-004-07