S1D13506 Configuration - Epson S1D13506 Technical Manual

Page 12

4.2 S1D13506 Configuration

S1D13506
Pin Name
MD[3:1] 111 = Toshiba TX3912 Host Bus Interface if MD11 = 1
MD4 Little Endian
MD5 WAIT# is active high (1 = insert wait state)
MD11 Alternate Host Bus Interface selected
MD12 BUSCLK input divided by two: use with DCLKOUT
MD15
WAIT# is always driven
= configuration for Toshiba TX3912 Host Bus Interface
S1D13506
X25B-G-010-02
The host interface control signals of the S1D13506 are asynchronous with respect to the
S1D13506 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks
should be the same, whether to use DCLKOUT as clock source, and whether an external or
internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13506 clock frequencies.
The S1D13506 also has internal CLKI dividers providing additional flexibility.
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings relevant to the Toshiba TX3912 Host
Bus Interface.
Table 4-1: S1D13506 Configuration for Direct Connection
Value on this pin at rising edge of RESET# is used to configure:
1 (V )
DD
Epson Research and Development
0 (V
Big Endian
WAIT# is active low (0 = insert wait state)
Primary Host Bus Interface selected
BUSCLK input not divided: use with external oscillator
WAIT# is floating if S1D13506 is not selected
Interfacing to the Toshiba MIPS TX3912 Processor
Vancouver Design Center
)
SS
Issue Date: 01/02/08