Table 7-8: Pc Card Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Clock frequency
CLK
T Clock period
CLK
t2 Clock pulse width high
t3 Clock pulse width low
A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either
t4
OE# = 0 or WE# = 0
t5 A[20:1], M/R# hold from rising edge of either OE# or WE#
t6 CS# hold from rising edge of either OE# or WE#
t7 Falling edge of either OE# or WE# to WAIT# driven low
t8 Rising edge of either OE# or WE# to WAIT# tri-state
D[15:0] setup to third CLK where CE1# = 0, CE2# = 0 and WE# = 0
t9
(write cycle)
t10 D[15:0] hold (write cycle)
t11 Falling edge OE# to D[15:0] driven (read cycle)
t12 D[15:0] setup to rising edge WAIT# (read cycle)
t13 Rising edge of OE# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-8: PC Card Timing

Parameter
3.0V 5.0V
Min Max Min Max
50 50
1/f 1/f
CLK CLK
6 6
6 6
4 3
0 0
0 0
2 21 2
3 14 2
0 0
0 0
10 8
0 0
7 34 5 17
X25B-A-001-12
Page 63
Units
MHz
ns
ns
ns
ns
ns
ns
9 ns
9 ns
ns
ns
ns
ns
ns
S1D13506