Nec V832 Configuration - Epson S1D13506 Technical Manual

Page 14

4.3 NEC V832 Configuration

S1D13506
X25B-G-012-03
The NEC V832 should access the S1D13506 in non-burst mode only. This is ensured by
using any one of the CS3 to CS6 lines to control the S1D13506 and setting that line to
respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is
used then bit 5 (CT5) of the BCTC register should be set to 1 (IO cycle).
The NEC V832 data bus should be programmed to use 16 bits as the maximum width for
S1D13506 bus transactions. This does not affect the width of other NEC V832 data bus
transactions. Data bus width is set in the NEC V832 DBC register. For example, if line CS4
is used then bit 4 (BW4) of the DBC register should be set to 1 (16-bit bus width).
Depending on bus clock frequencies, a different number of wait states may be required.
These need to be programmed into the NEC V832 PWC0 and PWC1 registers in the bit
field corresponding to the CSn line chosen for the S1D13506. For example, if CS3 is used
and one wait state is required, then bits 14-12 of the NEC V832 PWC0 register (WS3) must
be set to 001b (one wait state). If CS6 is used and no wait state is needed, then bits 11-8 of
the NEC V832 PWC1 register (WS6) must be set to 0000b (zero wait state).
The table below shows the recommended wait states depending on the bus clock frequency.
Table 4-2: NEC 832 Wait States vs. Bus Clock Frequency
V
Wait States Maximum Frequency (SDCLKOUT)
0
1
2
No idle state needs to be added. The NEC V832 PIC0 and PIC1 register bit field
corresponding to the CSn line chosen for the S1D13506 must be set to zero. For example,
if CS3 is used then bits 14-12 of the NEC V832 PIC0 register (IS3) must be set to 000b (no
idle state).
10.8MHz
32.6MHz
No limit
Interfacing to the NEC V832™ Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/08