Epson S1D13506 Technical Manual page 661

Epson Research and Development
Vancouver Design Center
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2-1: NEC VR4121 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: NEC VR4121 to S1D13506 Configuration Schematic . . . . . . . . . . . . . . . . . . . 12
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
List of Tables
List of Figures
Page 5
S1D13506
X25B-G-011-02