Table 4-3. Exception Priorities - IBM PowerPC 750GX User Manual

Table 4-3. Exception Priorities

Priority Exception
Asynchronous Exceptions (Interrupts)
0 System Reset
1 Machine Check
2 System Reset
3 SMI
4
5 PFM
6 DEC
7 TMI
Instruction Fetch Exceptions
0
Instruction Dispatch/Execution Exceptions
0 IABR
1
2
3 FPA
4
5 DSI
6 Alignment
7 DSI
8 DSI
9 DSI
10 DSI
Post Instruction Execution Exceptions
11 Trace
1. Even though DSISR(5) and DSISR(11) are set by different priority exceptions, both bits can be set at the same time.
gx_04.fm.(1.2)
March 27, 2006
Cause
HRESET, POR
TEA, 60x address-parity error, 60x data-parity error, L2 ECC double-bit error, MCP, L2-tag
parity error, data-tag parity error, instruction-tag parity error, instruction-cache parity error,
data-cache parity error, or locked L2 snoop hit
SRESET
SMI (system management exception)
EI INT (External Exception)
Performance-monitor exception
Decrementer exception
Thermal-management exception
ISI Instruction storage exception
Instruction address breakpoint exception
Program exception due to:
1. Illegal instruction
PI
2. Privileged instruction
3. Trap
SC System call
Floating-point unavailable exception
PI Program exception due to floating-point enabled exception
Data-storage exception due to eciwx, ecowx with the enable bit of the External Access Reg-
ister cleared (EAR[E] = 0) (bit 11 of DSISR)
Alignment exception due to:
• Floating point not word aligned
• lmw, stmw, lwarx, or stwcx not word-aligned
• Either eciwx or ecowx not word-aligned
• Multiple or string access with the little-endian bit set.
• dcbz to write-through or cache-inhibited page or cache is disabled.
Data-storage exception due to a block-address-translation (BAT) page-protection violation
Data-storage exception due to:
• Any access except cache operations to a segment where SR[T] = 1
• An access that crosses from an SR[T] = 0 segment to an SR[T} = 1 segment
These exceptions are indicated by DSISR[5] = 1.
Data-storage exception due to a translation lookaside buffer (TLB) page-protection violation
Data-storage exception due to a Data Address Breakpoint Register (DABR) address match
Trace exception due to:
MSR[SE] = 1 or (MSR[BE] = 1 for branches
IBM PowerPC 750GX and GL RISC Microprocessor
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User's Manual
Exceptions
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