Serirqc-Serial Irq Control Register (Function 0); Tom-Top Of Memory Register (Function 0) - Intel 460GX Software Developer’s Manual

LPC/FWH Interface Configuration
11.1.13 SerIRQC–Serial IRQ Control Register (Function 0)
Address Offset:
Default Value:
Attribute:
This register controls the Start Frame Pulse Width generated on the Serial Interrupt signal
(SERIRQ).
Bit
7
6
5:2
1:0
11.1.14 TOM–Top of Memory Register (Function 0)
Address Offset:
Default Value:
Attribute:
This register enables the forwarding of DMA memory cycles to the PCI Bus and sets the top of
main memory accessible by DMA devices. In addition, this register controls the forwarding of
DMA accesses to the lower firmware region (E0000–EFFFFh) and the 512–640 KByte main
memory region (80000–9FFFFh).
Bit
7:4
3
2
1
0
11-6
64h
10h
R/W
Serial IRQ Enable. 1=Serial Interrupts are enabled. 0=Serial Interrupts disabled.
Serial IRQ Mode Select. When this bit is a "1", the serial IRQ machine will be in continuous mode.
When this bit is a "0", the serial IRQ machine will be in quiet mode. When setting the SIRQEN bit,
this bit must also be written as a one so that the first action of the serial IRQ machine will be a start
frame.
Serial IRQ Frame Size. These bits select the frame size used by the Serial IRQ logic. The default
is 0100b indicating a frame size of 21 (17+4). These bits are readable and writeable, however the
only programmed value supported by the IFB is 0100b. All other frame sizes are unsupported.
Start Frame Pulse Width. These bits define the Start Frame pulse width generated by the Serial
Interrupt control logic.
Bits[1:0] Pulse Width (PCI Clocks)
00 4 Clocks
01 6 Clocks
10 8 Clocks
11 Reserved
69h
02h
Read/Write
Top Of Memory. The top of memory can be assigned in 1 Mbyte increments from 1–16 Mbytes.
DMA accesses within this region, and not in the memory hole region, are forwarded to PCI.
Bits[7:4] Top of Memory
0000 1 Mbyte
0001 2 Mbyte
0010 3 Mbyte
0011 4 Mbyte
0100 5 Mbyte
0101 6 Mbyte
Note that the IFB only supports a main memory hole at the top of 16 Mbytes. Thus, If a 1 Mbyte
memory hole is created for the Host-to-PCI Bridge DRAM controller between 15 and 16 Mbytes, the
IFB Top Of Memory should be set at 15 Mbytes.
Reserved. Must be set to '0'.
Reserved. Must be set to '0'.
Reserved. Must be set to '0'.
Reserved.
Description
Description
Bits[7:4] Top of Memory
0110 7 Mbyte
0111 8 Mbyte
1000 9 Mbyte
1001 10 Mbyte
1010 11 Mbyte
Intel® 460GX Chipset Software Developer's Manual
Bits[7:4] Top of Memory
1011 12 Mbyte
1100 13 Mbyte
1101 14 Mbyte
1110 15 Mbyte
1111 16 Mbyte