Pmbaseu6 - Prefetchable Memory Base Address Upper; Pmbaseu6 - Prefetchable Memory Base Address Upper Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.19

PMBASEU6 - Prefetchable Memory Base Address Upper

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range is aligned to a 1-MB boundary.
Table 42.

PMBASEU6 - Prefetchable Memory Base Address Upper Register

Default
Bit Access
31:0 RW 00000000h
April 2010
Document Number: 323178-002
RST/
Value PWR
Core Prefetchable Memory Base Address (MBASEU)
Corresponds to A[63:32] of the lower limit of the prefetchable
memory range that is passed to PCI Express-G.
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
0/6/0/PCI
28-2Bh
00000000h
RW
32 bits
Description
®
Celeron
®
Processor P4500, P4505 Series
Datasheet Addendum
99