Pcicmd6 - Pci Command; Pcicmd6 - Pci Command Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

6.2.3

PCICMD6 - PCI Command

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 26. PCICMD6 - PCI Command Register (Sheet 1 of 2)
Bit Access Default
15:11 RO
10 RW
9 RO
8 RW
7 RO
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
86
RST/
Value PWR
00h Core Reserved
0b Core INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt
1 = This device is prevented from generating interrupt
Only affects interrupts generated by the device (PCI INTA from
a PME or Hot Plug event) controlled by this command register.
It does not affect upstream MSIs, upstream PCI INTA-INTD
assert and deassert messages.
0b Core Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. hard wired to 0.
0b Core SERR# Message Enable (SERRE1)
Controls Device 6 SERR# messaging. The processor
communicates the SERR# condition by sending an SERR
message to the PCH. This bit, when set, enables reporting of
non-fatal and fatal errors detected by the device to the Root
Complex. Note that errors are reported if enabled either
through this bit or through the PCI-Express specific bits in the
Device Control Register.
In addition, for Type 1 configuration space header devices, this
bit, when set, enables transmission by the primary interface of
ERR_NONFATAL and ERR_FATAL error messages forwarded
from the secondary interface. This bit does not affect the
transmission of forwarded ERR_COR messages.
0 = The SERR message is generated by the processor for
1 = The processor is enabled to generate SERR messages
0b Core Reserved
Not Applicable or Implemented. Hard wired to 0.
0/6/0/PCI
4-5h
0000h
RO; RW
16 bits
Description
messages.
messages. Any INTA emulation interrupts already asserted
must be de-asserted when this bit is set.
Device 6 only under conditions enabled individually
through the Device Control Register.
which is sent to the PCH for specific Device 6 error
conditions generated/detected on the primary side of the
virtual PCI to PCI bridge (not those received by the
secondary side). The status of SERRs generated is reported
in the PCISTS6 register.
® ®
Celeron Processor P4505, U3405 Series
Processor Configuration Registers
August 2010
Document Number: 323178-003