Initialization Command Word 1 (Icw1); Initialization Command Word 1 Register (Icw1) - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
9.3.3

Initialization Command Word 1 (ICW1)

Initialization begins with writing ICW1. Use ICW1 to select the interrupt request triggering type
(level or edge). The following actions occur within an 82C59A module when its ICW1 is written:
•
The interrupt mask register is cleared, enabling all interrupt request signals.
•
The IR7 signal is assigned the lowest interrupt level (default).
•
Special mask mode is disabled.
Initialization Command Word 1
ICW1 (master and slave)
(write only)
7
0 0
Bit Bit
Number Mnemonic
7–5 —
4 RSEL1
3 LS
2–1 —
0 —
NOTE: The 82C59A must be initialized before it can be used. After reset, the 82C59A register states are
undefined. The 82C59A modules must be initialized before the IF flag in the core FLAG register is
set. All peripherals that use interrupts connected to the ICU must be initialized before initializing
the ICU.
Figure 9-8. Initialization Command Word 1 Register (ICW1)
9-20
0 RSEL1
Clear these bits to guarantee device operation.
Register Select 1 (Also see OCW2 and OCW3):
ICW1, OCW2, and OCW3 are accessed through the same addresses.
0 = OCW2 or OCW3 is accessed (Figure 9-13 and Figure 9-15).
1 = ICW1 register is accessed.
Level/Edge Sensitive:
0 = Selects edge-triggered IR input signals.
1 = Selects level-sensitive IR input signals.
All internal peripherals interface with the 82C59As in edge-triggered
mode only. This is compatible with the PC/AT bus specification. Each
source signal initiates an interrupt request by making a low-to-high
transition. External peripherals interface with the 8259As in edge-
triggered or level-sensitive mode. The modes are selected for the
device, not for individual interrupts.
NOTE: If an internal peripheral interrupt is used, the 8259A that the
interrupt is connected to must be programmed for edge-triggered
interrupts.
Clear these bits to guarantee device operation.
Set this bit to guarantee device operation.
master
Expanded Addr: F020H
ISA Addr: 0020H
Reset State: XXH
LS 0
Function
slave
F0A0H
00A0H
XXH
0
0 1