Table of Contents
Advertisement
Interfaces
2.2.2
PCI Express Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-6. PCI Express Related Register Structures in the Processor
PCI
Express
Device
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (which consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(which consists of the remaining configuration space). The PCI-compatible region can
be accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3
PCI Express Ports and Bifurcation
The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port that
can be:
•
configured at narrower widths
•
bifurcated into two x8 PCI Express ports that may train to narrower widths
The PEG port is being designed to be compliant with the PCI Express Base
Specification, Revision 2.0.
Datasheet
PEG0
representing
Express port
(Device 1)
PCI-PCI
PCI
Bridge
Compatible
Host Bridge
root PCI
Device
(Device 0)
DMI
27
Advertisement
Table of Contents
