Figure 289. Counter Timing Diagram, Internal Clock Divided By N; Figure 290. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow) - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0351
General-purpose timers (TIM2/TIM3/TIM4/TIM5)

Figure 289. Counter timing diagram, internal clock divided by N

Figure 290. Counter timing diagram, Update event with ARPE=1 (counter underflow)

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