Gpio Dip Switch - Xilinx VCU110 User Manual

GPIO DIP Switch

[Figure 1-2, callout 26]
Figure 1-21 shows the GPIO DIP switch circuit.
X-Ref Target - Figure 1-21
Table 1-49 lists the GPIO Connections to FPGA U1.
Table 1-49: VCU110 GPIO Connections to FPGA U1
FPGA Pin (U1)
N25
N22
M22
M26
M25
P24
N24
N23
AT11
AY13
AM16
BC16
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
GPIO_DIP_SW3
GPIO_DIP_SW2
GPIO_DIP_SW1
GPIO_DIP_SW0
1
2
R40
1
4.70KΩ
1/16W
2
1%
GND
Figure 1-21: CPU GPIO DIP Switch
Schematic Net Name
GPIO LEDs (Active-High)
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
GPIO_LED_4
GPIO_LED_5
GPIO_LED_6
GPIO_LED_7
Directional Pushbuttons (Active-High)
GPIO_SW_N
GPIO_SW_E
GPIO_SW_W
GPIO_SW_S
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Chapter 1: VCU110 Evaluation Board Features
SDA04H1SBD
1
2
3
4
SW12
R41 R51
1
4.70KΩ 4.70KΩ
1/16W 1/16W
2
1% 1%
R50
1
4.70KΩ
1/16W
2
1%
I/O Standard
(1)
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS12
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
VCC1V2_FPGA
8
7
6
5
GPIO
DS7.1
DS6.1
DS8.1
DS9.1
DS10.1
DS33.1
DS32.1
DS31.1
SW10.3
SW9.3
SW6.3
SW8.3
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