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The connections between the HMC component U160 Bank L0 and XCVU190 GTH Quads
229-232 are listed in
capacitor coupled.
Table 1-8: HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_229
MGTHTXN0_229
MGTHRXP0_229
MGTHRXN0_229
MGTHTXP1_229
MGTHTXN1_229
MGTHRXP1_229
MGTHRXN1_229
MGTHTXP2_229
GTH
MGTHTXN2_229
Quad
MGTHRXP2_229
229
MGTHRXN2_229
MGTHTXP3_229
MGTHTXN3_229
MGTHRXP3_229
MGTHRXN3_229
MGTREFCLK0P_229
MGTREFCLK0N_229
MGTREFCLK1P_229
MGTREFCLK1N_229
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Table
1-8. The nets with _C_P or _C_N in their net names are series
FPGA
(U1)
Schematic Net Name
Pin
R7
HMC_L0TX_12_P
R6
HMC_L0TX_12_N
R2
HMC_L0RX_12_C_P
R1
HMC_L0RX_12_C_N
P9
HMC_L0TX_9_P
P8
HMC_L0TX_9_N
P4
HMC_L0RX_9_C_P
P3
HMC_L0RX_9_C_N
N7
HMC_L0TX_13_P
N6
HMC_L0TX_13_N
N2
HMC_L0RX_13_C_P
N1
HMC_L0RX_13_C_N
M9
HMC_L0TX_8_P
M8
HMC_L0TX_8_N
M4
HMC_L0RX_8_C_P
M3
HMC_L0RX_8_C_N
U11
NA
U10
NA
T13
NA
T12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
G18
G17
E24
E23
F19
F18
F23
F22
A16
A15
D17
D16
A24
A23
C18
C17
NA
NA
NA
NA
Send Feedback
Connected Pin
Connected
Name
Device
L0RXP_0
L0RXN_0
L0TXP_0
L0TXN_0
L0RXP_1
L0RXN_1
L0TXP_1
L0TXN_1
HMC
U160
L0RXP_2
L0RXN_2
L0TXP_2
L0TXN_2
L0RXP_3
L0RXN_3
L0TXP_3
L0TXN_3
NA
NA
NA
NA
NA
26
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