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Table 1-38: VCU110 FPGA U1 GTH Quad 233 Connections
FPGA (U1)
FPGA (U1) Pin Name
MGTHTXP0_233
MGTHTXN0_233
MGTHRXP0_233
MGTHRXN0_233
MGTHTXP1_233
MGTHTXN1_233
MGTHRXP1_233
MGTHRXN1_233
MGTHTXP2_233
MGTHTXN2_233
MGTHRXP2_233
MGTHRXN2_233
MGTHTXP3_233
MGTHTXN3_233
MGTHRXP3_233
MGTHRXN3_233
MGTREFCLK0P_233
MGTREFCLK0N_233
MGTREFCLK1P_233
MGTREFCLK1N_233
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
For additional information on GTH transceivers, see UltraScale FPGAs GTH Transceivers User
Guide (UG576)
Also see UltraScale FPGAs Transceivers Wizard Product Guide for Vivado Design Suite
(PG182)
[Ref
6].
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
D9
PCIE_CABLE_TX3_C_P
D8
PCIE_CABLE_TX3_C_N
D14
PCIE_CABLE_RX3_P
D13
PCIE_CABLE_RX3_N
C11
PCIE_CABLE_TX2_C_P
C10
PCIE_CABLE_TX2_C_N
C16
PCIE_CABLE_RX2_P
C15
PCIE_CABLE_RX2_N
B9
PCIE_CABLE_TX1_C_P
B8
PCIE_CABLE_TX1_C_N
B14
PCIE_CABLE_RX1_P
B13
PCIE_CABLE_RX1_N
A11
PCIE_CABLE_TX0_C_P
A10
PCIE_CABLE_TX0_C_N
A16
PCIE_CABLE_RX0_P
A15
PCIE_CABLE_RX0_N
J11
PCIE_CABLE_CLK_C_P
J10
PCIE_CABLE_CLK_C_N
H13
NA
H12
NA
[Ref
7].
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin Number
(2)
A11
(2)
A12
B11
B12
(2)
A8
(2)
A9
B8
B9
(2)
A5
(2)
A6
B5
B6
(2)
A2
(2)
A3
B2
B3
(2)
A14
CREFCLKP
(2)
A15
CREFCLKN
NA
NA
Connected
Name
Device
PETP3
PETN3
PERP3
PERN3
PETP2
PETN2
PERP2
PERN2
PETP1
PCIe cable
connector J136
PETN1
PERP1
PERN1
PETP0
PETN0
PERP0
PERN0
NA
NA
NA
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