Xilinx VCU110 User Manual page 139

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VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
IOSTANDARD SSTL12
PACKAGE_PIN L20
IOSTANDARD SSTL12
PACKAGE_PIN L18
IOSTANDARD SSTL12
PACKAGE_PIN J16
IOSTANDARD SSTL12
PACKAGE_PIN L19
IOSTANDARD SSTL12
PACKAGE_PIN K18
IOSTANDARD SSTL12
PACKAGE_PIN M20
IOSTANDARD SSTL12
PACKAGE_PIN K19
IOSTANDARD SSTL12
PACKAGE_PIN N19
IOSTANDARD SSTL12
PACKAGE_PIN M16
IOSTANDARD SSTL12
PACKAGE_PIN M17
IOSTANDARD SSTL12
PACKAGE_PIN N20
IOSTANDARD SSTL12
PACKAGE_PIN P16
IOSTANDARD SSTL12
PACKAGE_PIN M15
IOSTANDARD SSTL12
PACKAGE_PIN P17
IOSTANDARD SSTL12
PACKAGE_PIN P20
IOSTANDARD SSTL12
PACKAGE_PIN P19
IOSTANDARD SSTL12
PACKAGE_PIN L16
IOSTANDARD SSTL12
PACKAGE_PIN N17
IOSTANDARD SSTL12
PACKAGE_PIN A21
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_DK0_N"]
PACKAGE_PIN B21
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_DK0_P"]
PACKAGE_PIN C18
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_DK1_N"]
PACKAGE_PIN C19
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_DK1_P"]
PACKAGE_PIN J17
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_QK0_N"]
PACKAGE_PIN K17
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_QK0_P"]
PACKAGE_PIN M18
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_QK1_N"]
PACKAGE_PIN N18
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_QK1_P"]
PACKAGE_PIN J15
IOSTANDARD SSTL12
PACKAGE_PIN D19
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_CK_N"]
PACKAGE_PIN D20
IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_18B_CK_P"]
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Appendix D: Master Constraints File Listing
[get_ports "RLD3_18B_DQ1"]
[get_ports "RLD3_18B_DQ2"]
[get_ports "RLD3_18B_DQ2"]
[get_ports "RLD3_18B_DQ3"]
[get_ports "RLD3_18B_DQ3"]
[get_ports "RLD3_18B_DQ4"]
[get_ports "RLD3_18B_DQ4"]
[get_ports "RLD3_18B_DQ5"]
[get_ports "RLD3_18B_DQ5"]
[get_ports "RLD3_18B_DQ6"]
[get_ports "RLD3_18B_DQ6"]
[get_ports "RLD3_18B_DQ7"]
[get_ports "RLD3_18B_DQ7"]
[get_ports "RLD3_18B_DQ8"]
[get_ports "RLD3_18B_DQ8"]
[get_ports "RLD3_18B_DQ9"]
[get_ports "RLD3_18B_DQ9"]
[get_ports "RLD3_18B_DQ10"]
[get_ports "RLD3_18B_DQ10"]
[get_ports "RLD3_18B_DQ11"]
[get_ports "RLD3_18B_DQ11"]
[get_ports "RLD3_18B_DQ12"]
[get_ports "RLD3_18B_DQ12"]
[get_ports "RLD3_18B_DQ13"]
[get_ports "RLD3_18B_DQ13"]
[get_ports "RLD3_18B_DQ14"]
[get_ports "RLD3_18B_DQ14"]
[get_ports "RLD3_18B_DQ15"]
[get_ports "RLD3_18B_DQ15"]
[get_ports "RLD3_18B_DQ16"]
[get_ports "RLD3_18B_DQ16"]
[get_ports "RLD3_18B_DQ17"]
[get_ports "RLD3_18B_DQ17"]
[get_ports "RLD3_18B_DM0"]
[get_ports "RLD3_18B_DM0"]
[get_ports "RLD3_18B_DM1"]
[get_ports "RLD3_18B_DM1"]
[get_ports "RLD3_18B_DK0_N"]
[get_ports "RLD3_18B_DK0_P"]
[get_ports "RLD3_18B_DK1_N"]
[get_ports "RLD3_18B_DK1_P"]
[get_ports "RLD3_18B_QK0_N"]
[get_ports "RLD3_18B_QK0_P"]
[get_ports "RLD3_18B_QK1_N"]
[get_ports "RLD3_18B_QK1_P"]
[get_ports "RLD3_18B_QVLD0"]
[get_ports "RLD3_18B_QVLD0"]
[get_ports "RLD3_18B_CK_N"]
[get_ports "RLD3_18B_CK_P"]
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