Xilinx VCU110 User Manual page 136

# Common Alarm and Reset Nets SI5328 U57, U179, U181
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# MEMORY
# QDR2 18-bit
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VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN M23
IOSTANDARD LVCMOS12
PACKAGE_PIN AW21
IOSTANDARD LVCMOS18
PACKAGE_PIN BA22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AY24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AW23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AV24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AW22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BB24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BE23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BD23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BC23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BE24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BF22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BF21
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BC24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BB23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BE22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BD22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BB22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BA24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN BA25
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AV23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AY25
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AY22
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AM23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AM24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AN23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AP22
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Appendix D: Master Constraints File Listing
[get_ports "SI5328_INT_ALM_LS"]
[get_ports "SI5328_INT_ALM_LS"]
[get_ports "SI5328_RST_LS"]
[get_ports "SI5328_RST_LS"]
[get_ports "QDR2_18B_A0"]
[get_ports "QDR2_18B_A0"]
[get_ports "QDR2_18B_A1"]
[get_ports "QDR2_18B_A1"]
[get_ports "QDR2_18B_A2"]
[get_ports "QDR2_18B_A2"]
[get_ports "QDR2_18B_A3"]
[get_ports "QDR2_18B_A3"]
[get_ports "QDR2_18B_A4"]
[get_ports "QDR2_18B_A4"]
[get_ports "QDR2_18B_A5"]
[get_ports "QDR2_18B_A5"]
[get_ports "QDR2_18B_A6"]
[get_ports "QDR2_18B_A6"]
[get_ports "QDR2_18B_A7"]
[get_ports "QDR2_18B_A7"]
[get_ports "QDR2_18B_A8"]
[get_ports "QDR2_18B_A8"]
[get_ports "QDR2_18B_A9"]
[get_ports "QDR2_18B_A9"]
[get_ports "QDR2_18B_A10"]
[get_ports "QDR2_18B_A10"]
[get_ports "QDR2_18B_A11"]
[get_ports "QDR2_18B_A11"]
[get_ports "QDR2_18B_A12"]
[get_ports "QDR2_18B_A12"]
[get_ports "QDR2_18B_A13"]
[get_ports "QDR2_18B_A13"]
[get_ports "QDR2_18B_A14"]
[get_ports "QDR2_18B_A14"]
[get_ports "QDR2_18B_A15"]
[get_ports "QDR2_18B_A15"]
[get_ports "QDR2_18B_A16"]
[get_ports "QDR2_18B_A16"]
[get_ports "QDR2_18B_A17"]
[get_ports "QDR2_18B_A17"]
[get_ports "QDR2_18B_A18"]
[get_ports "QDR2_18B_A18"]
[get_ports "QDR2_18B_A19"]
[get_ports "QDR2_18B_A19"]
[get_ports "QDR2_18B_A20"]
[get_ports "QDR2_18B_A20"]
[get_ports "QDR2_18B_A21"]
[get_ports "QDR2_18B_A21"]
[get_ports "QDR2_18B_D0"]
[get_ports "QDR2_18B_D0"]
[get_ports "QDR2_18B_D1"]
[get_ports "QDR2_18B_D1"]
[get_ports "QDR2_18B_D2"]
[get_ports "QDR2_18B_D2"]
[get_ports "QDR2_18B_D3"]
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