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Table 1-35: VCU110 FPGA U1 GTH Quad 230 Connections
FPGA
FPGA (U1) Pin Name
(U1)
MGTHTXP0_230
MGTHTXN0_230
MGTHRXP0_230
MGTHRXN0_230
MGTHTXP1_230
MGTHTXN1_230
MGTHRXP1_230
MGTHRXN1_230
MGTHTXP2_230
MGTHTXN2_230
MGTHRXP2_230
MGTHRXN2_230
MGTHTXP3_230
MGTHTXN3_230
MGTHRXP3_230
MGTHRXN3_230
MGTREFCLK0P_230
MGTREFCLK0N_230
MGTREFCLK1P_230
MGTREFCLK1N_230
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
L7
HMC_L0TX_10_P
L6
HMC_L0TX_10_N
L2
HMC_L0RX_10_C_P
L1
HMC_L0RX_10_C_N
K9
HMC_L0TX_14_P
K8
HMC_L0TX_14_N
K4
HMC_L0RX_14_C_P
K3
HMC_L0RX_14_C_N
J7
HMC_L0TX_0_P
J6
HMC_L0TX_0_N
J2
HMC_L0RX_0_C_P
J1
HMC_L0RX_0_C_N
H9
HMC_L0TX_1_P
H8
HMC_L0TX_1_N
H4
HMC_L0RX_1_C_P
H3
HMC_L0RX_1_C_N
R11
HMC_SI5328_OUT2_BUF1_C_P
R10
HMC_SI5328_OUT2_BUF1_C_N
P13
NA
P12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin
Number
C30
L0RXP_10
C29
L0RXN_10
(2)
G22
L0TXP_10
(2)
G21
L0TXN_10
F27
L0RXP_14
F26
L0RXN_14
(2)
G30
L0TXP_14
(2)
G29
L0TXN_14
G18
G17
(2)
E24
(2)
E23
F19
F18
(2)
F23
(2)
F22
(2)
35
CKOUT2_P
(2)
34
CKOUT2_N
NA
NA
Connected
Name
Device
HMC
U160
L0RXP_0
L0RXN_0
L0TXP_0
L0TXN_0
L0RXP_1
L0RXN_1
L0TXP_1
L0TXN_1
SI5328
U57
NA
NA
NA
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