Examax Backplane Connector - Xilinx VCU110 User Manual

ExaMAX Backplane Connector

[Figure 1-2, callout 43]
The VCU110 board provides an FCI ExaMAX backplane connector at J116. Two FPGA U1 GTY
Quads (121 and 120) implement eight differential transmit/receive pair channels.
The ExaMAX J116 to FPGA U1 connections are detailed in
Table 1-55: VCU110 ExaMAX J116 to FPGA U1 GTY Quads 121-120 Connections
ExaMAX
ExaMAX J116
J116 Pin
Pin Number
Name
TX1_P
TX1_N
RX1_P
RX1_N
TX2_P
TX2_N
RX2_P
RX2_N
TX3_P
TX3_N
RX3_P
RX3_N
TX4_P
TX4_N
RX4_P
RX4_N
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net
(1)
Name
K4 EXAMAX_TX1_P
L4 EXAMAX_TX1_N
B4 EXAMAX_RX1_P
C4 EXAMAX_RX1_N
H4 EXAMAX_TX2_P
I4 EXAMAX_TX2_N
E4 EXAMAX_RX2_P
F4 EXAMAX_RX2_N
L5 EXAMAX_TX3_P
M5 EXAMAX_TX3_N
C5 EXAMAX_RX3_P
D5 EXAMAX_RX3_N
I5 EXAMAX_TX4_P
J5 EXAMAX_TX4_N
F5 EXAMAX_RX4_P
G5 EXAMAX_RX4_N
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Chapter 1: VCU110 Evaluation Board Features
Table
FPGA (U1) FPGA (U1) Pin
Pin Name
AY38 MGTYTXP3_121
AY39 MGTYTXN3_121
AY43 MGTYRXP3_121
AY44 MGTYRXN3_121
BA40 MGTYTXP2_121
BA41 MGTYTXN2_121
BA45 MGTYRXP2_121
BA46 MGTYRXN2_121
BB38 MGTYTXP1_121
BB39 MGTYTXN1_121
BB43 MGTYRXP1_121
BB44 MGTYRXN1_121
BC40 MGTYTXP0_121
BC41 MGTYTXN0_121
BC45 MGTYRXP0_121
BC46 MGTYRXN0_121
1-55.
MGT Quad
GTY Quad 121
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