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Table 1-23: VCU110 FPGA U1 GTY Quad 131 Connections
FPGA (U1) Pin Name
MGTYTXP0_131
MGTYTXN0_131
MGTYRXP0_131
MGTYRXN0_131
MGTYTXP1_131
MGTYTXN1_131
MGTYRXP1_131
MGTYRXN1_131
MGTYTXP2_131
MGTYTXN2_131
MGTYRXP2_131
MGTYRXN2_131
MGTYTXP3_131
MGTYTXN3_131
MGTYRXP3_131
MGTYRXN3_131
MGTREFCLK0P_131
MGTREFCLK0N_131
MGTREFCLK1P_131
MGTREFCLK1N_131
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic
(U1) Pin
Net Name
G40
ILKN_TX8_P
G41
ILKN_TX8_N
G45
ILKN_RX8_C_P
G46
ILKN_RX8_C_N
F38
ILKN_TX9_P
F39
ILKN_TX9_N
F43
ILKN_RX9_C_P
F44
ILKN_RX9_C_N
G36
ILKN_TX10_P
G37
ILKN_TX10_N
G31
ILKN_RX10_C_P
G32
ILKN_RX10_C_N
F34
ILKN_TX11_P
F35
ILKN_TX11_N
E31
ILKN_RX11_C_P
E32
ILKN_RX11_C_N
N36
ILKN_SI5328_OUT2_BUF3_C_P
N37
ILKN_SI5328_OUT2_BUF3_C_N
M34
NA
M35
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
F5
F6
(2)
G5
(2)
G6
H5
H6
(2)
J5
(2)
J6
F8
F9
(2)
G8
(2)
G9
H8
H9
(2)
J8
(2)
J9
(2)
35
(2)
34
NA
NA
Connected
Connected
Pin Name
Device
TX8_P
TX8_N
RX8_P
RX8_N
TX9_P
TX9_N
RX9_P
RX9_N
Interlaken
J121
TX10_P
TX10_N
RX10_P
RX10_N
TX11_P
TX11_N
RX11_P
RX11_N
CKOUT2_P
SI5328
U181
CKOUT2_N
NA
NA
NA
58
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