Appendix D: Master Constraints File Listing; Overview; Vcu110 Board Constraints File Listing - Xilinx VCU110 User Manual

Master Constraints File Listing

Overview

The master Xilinx design constraints (XDC) file template for the VCU110 board provides for
designs targeting the VCU110 evaluation board. Net names in the constraints file correlate
with net names on the latest VCU110 evaluation board schematic. Identify the appropriate
pins and replace the net names with net names in the user RTL. See Vivado Design Suite User
Guide: Using Constraints (UG903)
For detailed I/O standards information required for a particular interface, refer to the
constraint files generated by tools such as the memory interface generator (MIG) and base
system builder (BSB).
The FMC connectors J22 (HPC0) and J2 (HPC1) are connected to 1.8V VADJ banks. Because
different FMC cards implement different circuitry, the FMC bank I/O standards must be
uniquely defined by each customer.
The VCU110 constraints XDC file can be found on the
IMPORTANT:
VCU110 Development Kit

VCU110 Board Constraints File Listing

# CLOCKS
# System Clock 300 MHz
set_property
set_property
set_property
set_property
# System Clock 125 MHz
set_property
set_property
set_property
set_property
# Programmable User Clock 10-810 MHz 156.250 MHz power-up default)
set_property
set_property
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
[Ref 16]
website.
PACKAGE_PIN J24
IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK_300_P"]
PACKAGE_PIN H24
IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK_300_N"]
PACKAGE_PIN AV20
IOSTANDARD LVDS
PACKAGE_PIN AW20
IOSTANDARD LVDS
PACKAGE_PIN AY20
IOSTANDARD LVDS
www.xilinx.com
for more information.
Xilinx Virtex UltraScale FPGA
[get_ports "SYSCLK_300_P"]
[get_ports "SYSCLK_300_N"]
[get_ports "CLK_125MHZ_P"]
[get_ports "CLK_125MHZ_P"]
[get_ports "CLK_125MHZ_N"]
[get_ports "CLK_125MHZ_N"]
[get_ports "USER_SI570_CLOCK_P"]
[get_ports "USER_SI570_CLOCK_P"]
Appendix D
134
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