Xilinx VCU110 User Manual page 20

Table 1-5: RLD3 Memory U141 36-bit I/F to FPGA U1 Banks 70 and 71 (Cont'd)
FPGA (U1) Pin
D27
N28
M28
H28
H29
M31
L31
A26
G27
D25
C24
D24
F23
E23
B22
C23
G21
F24
A23
B23
C25
E24
B25
C22
A25
A24
G25
F25
F21
E22
H23
G23
H22
G22
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
RLD3_36B_QK0_N
RLD3_36B_QK1_P
RLD3_36B_QK1_N
RLD3_36B_QK2_P
RLD3_36B_QK2_N
RLD3_36B_QK3_P
RLD3_36B_QK3_N
RLD3_36B_QVLD0
RLD3_36B_QVLD1
RLD3_36B_A0
RLD3_36B_A3
RLD3_36B_A4
RLD3_36B_A5
RLD3_36B_A8
RLD3_36B_A9
RLD3_36B_A10
RLD3_36B_A13
RLD3_36B_A14
RLD3_36B_A17
RLD3_36B_A18
RLD3_36B_BA0
RLD3_36B_BA1
RLD3_36B_BA2
RLD3_36B_BA3
RLD3_36B_WE_B
RLD3_36B_REF_B
RLD3_36B_CK_P
RLD3_36B_CK_N
RLD3_36B_RESET_B
RLD3_36B_CS_B
RLD3_36B_DK0_P
RLD3_36B_DK0_N
RLD3_36B_DK1_P
RLD3_36B_DK1_N
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Chapter 1: VCU110 Evaluation Board Features
I/O Standard
SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
DIFF_SSTL12
DIFF_SSTL12
SSTL12
SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
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