Xilinx VCU110 User Manual page 146

# CFP4 MOD3
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# IIC
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# SGMII ETHERNET PHY
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# SYSTEM CONTROLLER
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# INTERLAKEN CONNECTOR
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VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN AV15
IOSTANDARD LVCMOS18
PACKAGE_PIN BD25
IOSTANDARD LVCMOS15
PACKAGE_PIN AP27
IOSTANDARD LVCMOS15
PACKAGE_PIN AP30
IOSTANDARD LVCMOS15
PACKAGE_PIN AV19
IOSTANDARD LVCMOS18
PACKAGE_PIN AV21
IOSTANDARD LVCMOS18
PACKAGE_PIN AR18
IOSTANDARD LVCMOS18
PACKAGE_PIN AY19
IOSTANDARD LVDS
PACKAGE_PIN AY18
IOSTANDARD LVDS
PACKAGE_PIN BC20
IOSTANDARD LVDS
PACKAGE_PIN BC19
IOSTANDARD LVDS
PACKAGE_PIN BA19
IOSTANDARD LVDS
PACKAGE_PIN BB19
IOSTANDARD LVDS
PACKAGE_PIN BB21
IOSTANDARD LVCMOS18
PACKAGE_PIN BB18
IOSTANDARD LVCMOS18
PACKAGE_PIN BC18
IOSTANDARD LVCMOS18
PACKAGE_PIN BC21
IOSTANDARD LVCMOS18
PACKAGE_PIN AU18
IOSTANDARD LVCMOS18
PACKAGE_PIN AM21
IOSTANDARD LVCMOS18
PACKAGE_PIN AV18
IOSTANDARD LVCMOS18
PACKAGE_PIN AW18
IOSTANDARD LVCMOS18
PACKAGE_PIN AN19
IOSTANDARD LVCMOS18
PACKAGE_PIN AN20
IOSTANDARD LVCMOS18
PACKAGE_PIN AW17
IOSTANDARD LVCMOS18
PACKAGE_PIN AN21
IOSTANDARD LVCMOS18
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Appendix D: Master Constraints File Listing
[get_ports "RX_LOS_MOD3_CFP4_LS"]
[get_ports "RX_LOS_MOD3_CFP4_LS"]
[get_ports "TX_DIS_MOD3_CFP4_LS"]
[get_ports "TX_DIS_MOD3_CFP4_LS"]
[get_ports "MOD_ABS_MOD3_CFP4_LS"]
[get_ports "MOD_ABS_MOD3_CFP4_LS"]
[get_ports "MOD_LOPWR_MOD3_CFP4_LS"]
[get_ports "MOD_LOPWR_MOD3_CFP4_LS"]
[get_ports "IIC_MAIN_SCL_LS"]
[get_ports "IIC_MAIN_SCL_LS"]
[get_ports "IIC_MAIN_SDA_LS"]
[get_ports "IIC_MAIN_SDA_LS"]
[get_ports "IIC_MUX_RESET_B_LS"]
[get_ports "IIC_MUX_RESET_B_LS"]
[get_ports "SGMIICLK_P"]
[get_ports "SGMIICLK_P"]
[get_ports "SGMIICLK_N"]
[get_ports "SGMIICLK_N"]
[get_ports "SGMII_RX_P"]
[get_ports "SGMII_RX_P"]
[get_ports "SGMII_RX_N"]
[get_ports "SGMII_RX_N"]
[get_ports "SGMII_TX_P"]
[get_ports "SGMII_TX_P"]
[get_ports "SGMII_TX_N"]
[get_ports "SGMII_TX_N"]
[get_ports "PHY_MDIO_LS"]
[get_ports "PHY_MDIO_LS"]
[get_ports "PHY_RESET_LS"]
[get_ports "PHY_RESET_LS"]
[get_ports "PHY_MDC_LS"]
[get_ports "PHY_MDC_LS"]
[get_ports "PHY_INT_LS"]
[get_ports "PHY_INT_LS"]
[get_ports "SYSCTLR_GPIO_5"]
[get_ports "SYSCTLR_GPIO_5"]
[get_ports "SYSCTLR_GPIO_6"]
[get_ports "SYSCTLR_GPIO_6"]
[get_ports "SYSCTLR_GPIO_7"]
[get_ports "SYSCTLR_GPIO_7"]
[get_ports "ILKN_FC_RX_CLK_LS"]
[get_ports "ILKN_FC_RX_CLK_LS"]
[get_ports "ILKN_FC_RX_DATA_LS"]
[get_ports "ILKN_FC_RX_DATA_LS"]
[get_ports "ILKN_FC_RX_SYNC_LS"]
[get_ports "ILKN_FC_RX_SYNC_LS"]
[get_ports "ILKN_FC_TX_CLK_LS"]
[get_ports "ILKN_FC_TX_CLK_LS"]
[get_ports "ILKN_FC_TX_DATA_LS"]
[get_ports "ILKN_FC_TX_DATA_LS"]
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