Xilinx VCU110 User Manual page 48

Quad 132:
• REFCLK0 - ILKN_SI5328_OUT2_BUF4_C_P/N (U196)
• REFCLK1 - not connected
• Four GTY transceivers allocated to ILKN_TX/RX[12:15]_P/N (J121)
Quad 133:
• REFCLK0 - ILKN_SI5328_OUT2_BUF5_C_P/N (U196)
• REFCLK1 - not connected
• Four GTY transceivers allocated to ILKN_TX/RX[16:19]_P/N (J121)
Table 1-13 through
124-133 connections, respectively.
Table 1-13: VCU110 FPGA U1 GTY Quad 120 Connections
FPGA (U1) Pin FPGA (U1)
Name
MGTYTXP0_120
MGTYTXN0_120
MGTYRXP0_120
MGTYRXN0_120
MGTYTXP1_120
MGTYTXN1_120
MGTYRXP1_120
MGTYRXN1_120
MGTYTXP2_120
MGTYTXN2_120
MGTYRXP2_120
MGTYRXN2_120
MGTYTXP3_120
MGTYTXN3_120
MGTYRXP3_120
MGTYRXN3_120
MGTREFCLK0P_120
MGTREFCLK0N_120
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Table 1-25 below list the VCU110 FPGA U1 GTY bank 120-122 and
Schematic Net Name
Pin
BF38 EXAMAX_TX8_P
BF39 EXAMAX_TX8_N
BF33 EXAMAX_RX8_P
BF34 EXAMAX_RX8_N
BE36 EXAMAX_TX7_P
BE37 EXAMAX_TX7_N
BD33 EXAMAX_RX7_P
BD34 EXAMAX_RX7_N
BE40 EXAMAX_TX6_P
BE41 EXAMAX_TX6_N
BF43 EXAMAX_RX6_P
BF44 EXAMAX_RX6_N
BD38 EXAMAX_TX5_P
BD39 EXAMAX_TX5_N
BD43 EXAMAX_RX5_P
BD44 EXAMAX_RX5_N
AN36 EXAMAX_SI5328_OUT1_BUF1_C_P
AN37 EXAMAX_SI5328_OUT1_BUF1_C_N
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Chapter 1: VCU110 Evaluation Board Features
Connected
Connected
(1)
Pin
Pin Name
Number
I7
J7
F7
G7
L7
M7
C7
D7
H6
I6
E6
F6
K6
L6
B6
C6
(2)
28 CKOUT1_P
(2)
29 CKOUT1_N
Send Feedback
Connected
Device
TX8_P
TX8_N
RX8_P
RX8_N
TX7_P
TX7_N
RX7_P
RX7_N
ExaMAX
J116
TX6_P
TX6_N
RX6_P
RX6_N
TX5_P
TX5_N
RX5_P
RX5_N
SI5328
U181
48