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Table 1-8: HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232 (Cont'd)
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_232
MGTHTXN0_232
MGTHRXP0_232
MGTHRXN0_232
MGTHTXP1_232
MGTHTXN1_232
MGTHRXP1_232
MGTHRXN1_232
MGTHTXP2_232
GTH
MGTHTXN2_232
Quad
MGTHRXP2_232
232
MGTHRXN2_232
MGTHTXP3_232
MGTHTXN3_232
MGTHRXP3_232
MGTHRXN3_232
MGTREFCLK0P_232
MGTREFCLK0N_232
MGTREFCLK1P_232
MGTREFCLK1N_232
Notes:
1. MGT connections I/O standard not applicable.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
(U1)
Schematic Net Name
Pin
E7
HMC_L0TX_3_P
E6
HMC_L0TX_3_N
E2
HMC_L0RX_3_C_P
E1
HMC_L0RX_3_C_N
E11
HMC_L0TX_15_P
E10
HMC_L0TX_15_N
D4
HMC_L0RX_15_C_P
D3
HMC_L0RX_15_C_N
C7
HMC_L0TX_5_P
C6
HMC_L0TX_5_N
C2
HMC_L0RX_5_C_P
C1
HMC_L0RX_5_C_N
A7
HMC_L0TX_7_P
A6
HMC_L0TX_7_N
B4
HMC_L0RX_7_C_P
B3
HMC_L0RX_7_C_N
L11
NA
L10
NA
K13
NA
K12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
H25
H24
J28
J27
G26
G25
H29
H28
F27
F26
G30
G29
E28
E27
A28
A27
NA
NA
NA
NA
Send Feedback
Connected Pin
Connected
Name
Device
L0RXP_12
L0RXN_12
L0TXP_12
L0TXN_12
L0RXP_13
L0RXN_13
L0TXP_13
L0TXN_13
HMC
U160
L0RXP_14
L0RXN_14
L0TXP_14
L0TXN_14
L0RXP_15
L0RXN_15
L0TXP_15
L0TXN_15
NA
NA
NA
NA
NA
29
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