Table of Contents
Advertisement
Table 1-54: VCU110 Interlaken Connector J121 Connections (Cont'd)
Interlaken
Interlaken
J121 Pin
Name
TX20_P
TX20_N
RX20_P
RX20_N
TX21_P
TX21_N
RX21_P
RX21_N
FC_TX_SYNC
FC_RX_SYNC
FC_TX_DATA
FC_RX_DATA
FC_TX_CLK
FC_RX_CLK
SPARE1
SPARE2
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. Level-shifted via U185 and U186.
The Interlaken protocol definition and recommended connector pinouts are in documents
located on the Interlaken Alliance website
For the Interlaken Protocol, refer to the Interlaken Look-Aside Protocol Definition v1.x, and
for connector pin-outs, refer to Interlaken Interop Recommendations v1.x. The protocol
definition document also discusses the flow control functions provided by the TX and RX
FC_CLK, FC_DATA and FC_SYNC connector pins.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J121 Pin
Schematic Net Name
Number
A17
NA
A18
NA
B17
NA
B18
NA
C17
NA
C18
NA
D17
NA
D18
NA
J17
ILKN_FC_TX_SYNC
J18
ILKN_FC_RX_SYNC
H17
ILKN_FC_TX_DATA
H18
ILKN_FC_RX_DATA
G17
ILKN_FC_TX_CLK
F17
ILKN_FC_RX_CLK
G18
GND
F18
GND
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
FPGA
FPGA (U1) Pin
(2)
(U1) Pin
Name
NA
NA
NA
NA
NA
NA
NA
NA
(3)
AM19
IO_L3P_T0L_N4
(3)
AN20
IO_L2P_T0L_N2
(3)
AN21
IO_L4N_T0U_N7
(3)
AN19
IO_L3N_T0L_N5
(3)
AW17
IO_L11N_T1U_N9
(3)
AW18
IO_L11P_T1U_N8
NA
NA
NA
NA
[Ref
34].
FPGA U1 Bank
NA
65
NA
107
Send Feedback
Advertisement
Table of Contents
