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Table 1-21: VCU110 FPGA U1 GTY Quad 129 Connections
FPGA (U1) Pin Name
(U1) Pin
MGTYTXP0_129
MGTYTXN0_129
MGTYRXP0_129
MGTYRXN0_129
MGTYTXP1_129
MGTYTXN1_129
MGTYRXP1_129
MGTYRXN1_129
MGTYTXP2_129
MGTYTXN2_129
MGTYRXP2_129
MGTYRXN2_129
MGTYTXP3_129
MGTYTXN3_129
MGTYRXP3_129
MGTYRXN3_129
MGTREFCLK0P_129
MGTREFCLK0N_129
MGTREFCLK1P_129
MGTREFCLK1N_129
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
R40
ILKN_TX0_P
R41
ILKN_TX0_N
R45
ILKN_RX0_C_P
R46
ILKN_RX0_C_N
P38
ILKN_TX1_P
P39
ILKN_TX1_N
P43
ILKN_RX1_C_P
P44
ILKN_RX1_C_N
N40
ILKN_TX2_P
N41
ILKN_TX2_N
N45
ILKN_RX2_C_P
N46
ILKN_RX2_C_N
M38
ILKN_TX3_P
M39
ILKN_TX3_N
M43
ILKN_RX3_C_P
M44
ILKN_RX3_C_N
U36
ILKN_SI5328_OUT2_BUF1_C_P
U37
ILKN_SI5328_OUT2_BUF1_C_N
T34
NA
T35
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
A2
A3
(2)
B2
(2)
B3
C2
C3
(2)
D2
(2)
D3
A5
A6
(2)
B5
(2)
B6
C5
C6
(2)
D5
(2)
D6
(2)
35
(2)
34
NA
NA
Connected
Connected
Pin Name
Device
TX0_P
TX0_N
RX0_P
RX0_N
TX1_P
TX1_N
RX1_P
RX1_N
Interlaken
J121
TX2_P
TX2_N
RX2_P
RX2_N
TX3_P
TX3_N
RX3_P
RX3_N
CKOUT2_P
SI5328
U181
CKOUT2_N
NA
NA
NA
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