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•
2 GT clocks
•
1 differential clock
•
159 ground and 15 power connections
The HPC1 J2 connections to FPGA U1 are shown in
Table 1-61: J2 VITA 57.1 FMC HPC1 Sections A and B to FPGA U1 Connections
J2
FMC
Schematic
HPC1
Net Name
Pin
A2
FMC_HPC1_DP1_M2C_P
A3
FMC_HPC1_DP1_M2C_N
A6
FMC_HPC1_DP2_M2C_P
A7
FMC_HPC1_DP2_M2C_N
A10
FMC_HPC1_DP3_M2C_P
A11
FMC_HPC1_DP3_M2C_N
A14
FMC_HPC1_DP4_M2C_P
A15
FMC_HPC1_DP4_M2C_N
A18
FMC_HPC1_DP5_M2C_P
A19
FMC_HPC1_DP5_M2C_N
A22
FMC_HPC1_DP1_C2M_P
A23
FMC_HPC1_DP1_C2M_N
A26
FMC_HPC1_DP2_C2M_P
A27
FMC_HPC1_DP2_C2M_N
A30
FMC_HPC1_DP3_C2M_P
A31
FMC_HPC1_DP3_C2M_N
A34
FMC_HPC1_DP4_C2M_P
A35
FMC_HPC1_DP4_C2M_N
A38
FMC_HPC1_DP5_C2M_P
A39
FMC_HPC1_DP5_C2M_N
Notes:
1. No I/O Standards are associated with MGT connections.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J2
U1
I/O
FMC
FPGA
Standard
HPC1
Pin
Pin
(1)
AP4
B1
(1)
AP3
B4
(1)
AN2
B5
(1)
AN1
B8
(1)
AM4
B9
(1)
AM3
B12
(1)
AW2
B13
(1)
AW1
B16
(1)
AV4
B17
(1)
AV3
B20
(1)
AP9
B21
(1)
AP8
B24
(1)
AN7
B25
(1)
AN6
B28
(1)
AM9
B29
(1)
AM8
B32
(1)
AW7
B33
(1)
AW6
B36
(1)
AV9
B37
(1)
AV8
B40
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Chapter 1:
VCU110 Evaluation Board Features
Table 1-61
through
Schematic
Net Name
NA
NA
NA
NA
NA
FMC_HPC1_DP7_M2C_P
FMC_HPC1_DP7_M2C_N
FMC_HPC1_DP6_M2C_P
FMC_HPC1_DP6_M2C_N
FMC_HPC1_GBTCLK1_M2C_P
FMC_HPC1_GBTCLK1_M2C_N
NA
NA
NA
NA
FMC_HPC1_DP7_C2M_P
FMC_HPC1_DP7_C2M_N
FMC_HPC1_DP6_C2M_P
FMC_HPC1_DP6_C2M_N
NA
Table
1-65.
U1
I/O
FPGA
Standard
Pin
NA
NA
NA
NA
NA
(1)
AT4
(1)
AT3
(1)
AU2
(1)
AU1
(1)
AF13
(1)
AF12
NA
NA
NA
NA
(1)
AT9
(1)
AT8
(1)
AU2
(1)
AU1
NA
116
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