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Table 1-9: HMC Memory U160 L1 I/F to FPGA U1 GTH Quads 225-228 (Cont'd)
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_227
MGTHTXN0_227
MGTHRXP0_227
MGTHRXN0_227
MGTHTXP1_227
MGTHTXN1_227
MGTHRXP1_227
MGTHRXN1_227
MGTHTXP2_227
GTH
MGTHTXN2_227
Quad
MGTHRXP2_227
227
MGTHRXN2_227
MGTHTXP3_227
MGTHTXN3_227
MGTHRXP3_227
MGTHRXN3_227
MGTREFCLK0P_227
MGTREFCLK0N_227
MGTREFCLK1P_227
MGTREFCLK1N_227
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
(U1)
Schematic Net Name
Pin
AC7
HMC_L1TX_11_P
AC6
HMC_L1TX_11_N
AC2
HMC_L1RX_11_C_P
AC1
HMC_L1RX_11_C_N
AB9
HMC_L1TX_14_P
AB8
HMC_L1TX_14_N
AB4
HMC_L1RX_14_C_P
AB3
HMC_L1RX_14_C_N
AA7
HMC_L1TX_15_P
AA6
HMC_L1TX_15_N
AA2
HMC_L1RX_15_C_P
AA1
HMC_L1RX_15_C_N
Y9
HMC_L1TX_13_P
Y8
HMC_L1TX_13_N
Y4
HMC_L1RX_13_C_P
Y3
HMC_L1RX_13_C_N
AA11
NA
AA10
NA
Y13
NA
Y12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
AJ23
AJ22
AJ19
AJ18
AH22
AH21
AK20
AK19
AG21
AG20
AJ27
AJ26
AF20
AF19
AG25
AG24
NA
NA
NA
NA
Send Feedback
Connected
Connected
Pin Name
Device
L1RXP_7
L1RXN_7
L1TXP_7
L1TXN_7
L1RXP_6
L1RXN_6
L1TXP_6
L1TXN_6
HMC
U160
L1RXP_5
L1RXN_5
L1TXP_5
L1TXN_5
L1RXP_4
L1RXN_4
L1TXP_4
L1TXN_4
NA
NA
NA
NA
NA
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