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Table 1-12: VCU110 Clock Sources to XCVU190 FPGA U1 Connections (Cont'd)
Clock Source
Reference
Schematic Net Name
Designator
and Pin
U180.11
CFP4_SI5328_OUT1_BUF2_C_P
U180.12
CFP4_SI5328_OUT1_BUF2_C_N
U180.13
CFP4_SI5328_OUT1_BUF3_C_P
U180.14
CFP4_SI5328_OUT1_BUF3_C_N
U180.15
CFP4_SI5328_OUT1_BUF4_C_P
U180.16
CFP4_SI5328_OUT1_BUF4_C_N
U184.9
EXAMAX_SI5328_OUT1_BUF1_C_P
U184.10
EXAMAX_SI5328_OUT1_BUF1_C_N
U184.11
EXAMAX_SI5328_OUT1_BUF2_C_P
U184.12
EXAMAX_SI5328_OUT1_BUF2_C_N
U196.5
ILKN_SI5328_OUT2_BUF1_C_P
U196.4
ILKN_SI5328_OUT2_BUF1_C_N
U196.32
ILKN_SI5328_OUT2_BUF2_C_P
U196.31
ILKN_SI5328_OUT2_BUF2_C_N
U196.30
ILKN_SI5328_OUT2_BUF3_C_P
U196.29
ILKN_SI5328_OUT2_BUF3_C_N
U196.28
ILKN_SI5328_OUT2_BUF4_C_P
U196.27
ILKN_SI5328_OUT2_BUF4_C_N
U196.26
ILKN_SI5328_OUT2_BUF5_C_P
U196.25
ILKN_SI5328_OUT2_BUF5_C_N
J87.19
BULLSEYE1_GTY_REFCLK0_C_P
J87.20
BULLSEYE1_GTY_REFCLK0_C_N
J87.1
BULLSEYE1_GTY_REFCLK1_C_P
J87.2
BULLSEYE1_GTY_REFCLK1_C_N
J122.19
BULLSEYE2_GTY_REFCLK0_C_P
J122.20
BULLSEYE2_GTY_REFCLK0_C_N
J122.1
BULLSEYE2_GTY_REFCLK1_C_P
J122.2
BULLSEYE2_GTY_REFCLK1_C_N
J136.A14
PCIE_CABLE_CLK_C_P
J136.A15
PCIE_CABLE_CLK_C_N
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Chapter 1:
I/O Standard
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www.xilinx.com
VCU110 Evaluation Board Features
Connected
Connection or FPGA
Pin
(U1) Bank
AE36
GTY 125 REFCLK0
AE37
AA36
GTY127 REFCLK0
AA37
W36
GTY128 REFCLK0
W37
AN36
GTY 120 REFCLK0
AN37
AL36
GTY 121 REFCLK0
AL37
U36
GTY 129 REFCLK0
U37
R36
GTY 130 REFCLK0
R37
N36
GTY 131 REFCLK0
N37
L36
GTY 132 REFCLK0
L37
J36
GTY 133 REFCLK0
J37
AC36
GTY 126 REFCLK0
AC37
AB34
GTY 126 REFCLK1
AB35
AG36
GTY 124 REFCLK0
AG37
AF34
GTY 124 REFCLK1
AF35
J11
GTH 233 REFCLK0
J10
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