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The HPC0 J22 connections to FPGA U1 are shown in
Table 1-56: J22 VITA 57.1 FMC HPC0 Sections A and B to FPGA U1 Connections
J22
FMC
Schematic
HPC0
Net Name
Pin
A2
FMC_HPC0_DP1_M2C_P
A3
FMC_HPC0_DP1_M2C_N
A6
FMC_HPC0_DP2_M2C_P
A7
FMC_HPC0_DP2_M2C_N
A10
FMC_HPC0_DP3_M2C_P
A11
FMC_HPC0_DP3_M2C_N
A14
FMC_HPC0_DP4_M2C_P
A15
FMC_HPC0_DP4_M2C_N
A18
FMC_HPC0_DP5_M2C_P
A19
FMC_HPC0_DP5_M2C_N
A22
FMC_HPC0_DP1_C2M_P
A23
FMC_HPC0_DP1_C2M_N
A26
FMC_HPC0_DP2_C2M_P
A27
FMC_HPC0_DP2_C2M_N
A30
FMC_HPC0_DP3_C2M_P
A31
FMC_HPC0_DP3_C2M_N
A34
FMC_HPC0_DP4_C2M_P
A35
FMC_HPC0_DP4_C2M_N
A38
FMC_HPC0_DP5_C2M_P
A39
FMC_HPC0_DP5_C2M_N
Notes:
1. No I/O Standards are associated with MGT connections.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J22
U1
I/O
FMC
FPGA
Standard
HPC0
Pin
Pin
(1)
BD14
B1
(1)
BD13
B4
(1)
BF4
B5
(1)
BF3
B8
(1)
BD4
B9
(1)
BD3
B12
(1)
BC2
B13
(1)
BC1
B16
(1)
BB4
B17
(1)
BB3
B20
(1)
BE11
B21
(1)
BE10
B24
(1)
BE7
B25
(1)
BE6
B28
(1)
BD9
B29
(1)
BD8
B32
(1)
BC7
B33
(1)
BC6
B36
(1)
BB9
B37
(1)
BB8
B40
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Chapter 1:
VCU110 Evaluation Board Features
Table 1-56
through
Schematic
Net Name
NA
NA
NA
NA
NA
FMC_HPC0_DP7_M2C_P
FMC_HPC0_DP7_M2C_N
FMC_HPC0_DP6_M2C_P
FMC_HPC0_DP6_M2C_N
FMC_HPC0_GBTCLK1_M2C_P
FMC_HPC0_GBTCLK1_M2C_N
NA
NA
NA
NA
FMC_HPC0_DP7_C2M_P
FMC_HPC0_DP7_C2M_N
FMC_HPC0_DP6_C2M_P
FMC_HPC0_DP6_C2M_N
NA
Send Feedback
Table
1-60.
U1
I/O
FPGA
Standard
Pin
(1)
AY4
(1)
AY3
(1)
BA2
(1)
BA1
(2)
(1)
AK13
(2)
(1)
AK12
(1)
AY9
(1)
AY8
(1)
BA7
(1)
BA6
NA
111
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