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Table 1-13: VCU110 FPGA U1 GTY Quad 120 Connections (Cont'd)
FPGA (U1) Pin
FPGA (U1)
Name
MGTREFCLK1P_120
MGTREFCLK1N_120
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
Table 1-14: VCU110 FPGA U1 GTY Quad 121 Connections
FPGA (U1) Pin
FPGA (U1)
Name
MGTYTXP0_121
MGTYTXN0_121
MGTYRXP0_121
MGTYRXN0_121
MGTYTXP1_121
MGTYTXN1_121
MGTYRXP1_121
MGTYRXN1_121
MGTYTXP2_121
MGTYTXN2_121
MGTYRXP2_121
MGTYRXN2_121
MGTYTXP3_121
MGTYTXN3_121
MGTYRXP3_121
MGTYRXN3_121
MGTREFCLK0P_121
MGTREFCLK0N_121
MGTREFCLK1P_121
MGTREFCLK1N_121
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
AM34
AM35
Schematic Net Name
Pin
BC40
EXAMAX_TX4_P
BC41
EXAMAX_TX4_N
BC45
EXAMAX_RX4_P
BC46
EXAMAX_RX4_N
BB38
EXAMAX_TX3_P
BB39
EXAMAX_TX3_N
BB43
EXAMAX_RX3_P
BB44
EXAMAX_RX3_N
BA40
EXAMAX_TX2_P
BA41
EXAMAX_TX2_N
BA45
EXAMAX_RX2_P
BA46
EXAMAX_RX2_N
AY38
EXAMAX_TX1_P
AY39
EXAMAX_TX1_N
AY43
EXAMAX_RX1_P
AY44
EXAMAX_RX1_N
AL36
EXAMAX_SI5328_OUT1_BUF2_C_P
AL37
EXAMAX_SI5328_OUT1_BUF2_C_N
AK34
AK35
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Number
NA
NA
Connected
(1)
Pin
Number
(2)
(2)
NA
NA
Connected
Connected
Pin
Pin Name
Device
NA
NA
NA
NA
Connected
Connected
Pin Name
Device
I5
TX4_P
J5
TX4_N
F5
RX4_P
G5
RX4_N
L5
TX3_P
M5
TX3_N
C5
RX3_P
D5
RX3_N
ExaMAX
J116
H4
TX2_P
I4
TX2_N
E4
RX2_P
F4
RX2_N
K4
TX1_P
L4
TX1_N
B4
RX1_P
C4
RX1_N
28
CKOUT_P
SI5328
U181
29
CKOUT_N
NA
NA
NA
NA
Send Feedback
NA
NA
49
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