Xilinx VCU110 User Manual page 119

Table 1-64: J2 VITA 57.1 FMC HPC1 Sections G and H to FPGA U1 Connections
J2
FMC
Schematic Net Name
HPC1
Pin
G2 NA
G3 NA
G6 FMC_HPC1_LA00_CC_P
G7 FMC_HPC1_LA00_CC_N
G9 FMC_HPC1_LA03_P
G10 FMC_HPC1_LA03_N
G12 FMC_HPC1_LA08_P
G13 FMC_HPC1_LA08_N
G15 NA
G16 NA
G18 NA
G19 NA
G21 NA
G22 NA
G24 NA
G25 NA
G27 NA
G28 NA
G30 NA
G31 NA
G33 NA
G34 NA
G36 NA
G37 NA
G39 VADJ_1V8_FPGA
Notes:
1. Also wired to System Controller U111.R12.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J2
U1
I/O FMC
FPGA
Standard HPC1
Pin
Pin
NA
NA H1
NA NA H2
AV33
LVCMOS18 H4
AV34
LVCMOS18 H5
AV36
LVCMOS18 H7
LVCMOS18 AW36 H8
AN32
LVCMOS18 H10
AP32
LVCMOS18 H11
NA H13
NA H14
NA H16
NA H17
NA H19
NA H20
NA H22
NA H23
NA H25
NA H26
NA H28
NA H29
NA H31
NA H32
NA H34
NA H35
H37
H38
H40
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Chapter 1: VCU110 Evaluation Board Features
Schematic Net Name
FMC_HPC1_VREF_A_M2C
(1)
FMC_HPC1_PRSNT_M2C_B
FMC_HPC1_CLK0_M2C_P
FMC_HPC1_CLK0_M2C_N
FMC_HPC1_LA02_P
FMC_HPC1_LA02_N
FMC_HPC1_LA04_P
FMC_HPC1_LA04_N
FMC_HPC1_LA07_P
FMC_HPC1_LA07_N
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VADJ_1V8_FPGA
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U1
I/O
FPGA
Standard
Pin
NA
NA
NA AP21
AU33
LVCMOS18
AU34
LVCMOS18
AR34
LVCMOS18
LVCMOS18 AT34
AP33
LVCMOS18
AR33
LVCMOS18
LVCMOS18 AV35
AW35
LVCMOS18
NA NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
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