Gpio Dip Switch; User Pmod Gpio Headers - Xilinx ZC706 User Manual

GPIO DIP Switch

Figure 1-27 shows the GPIO DIP switch circuit.
X-Ref Target - Figure 1-27
Table 1-30 lists the GPIO DIP switch connections to XC7Z045 AP SoC U1.
Table 1-30: GPIO DIP Switch Connections to XC7Z045 AP SoC at U1
XC7Z045 AP S0C (U1) Pin
AB17
AC16
AC17
AJ13

User PMOD GPIO Headers

[Figure 1-2, callout 26]
The ZC706 evaluation board GPIO 2 x 6 male headers J57 and J58 support Digilent Pmod
Peripheral Modules. J57 pins (IIC_PMOD_[0:7]) are connected to the TI TCA6416APWR I2C
expansion port device U16. J58 pins (PMOD1_[0:7]) are connected to the TI TXS0108E
3.3V-to-VADJ level-shifter U40.
See the Digilent website for information on Digilent Pmod Peripheral Modules
Information about the TCA641APWR and TXS0108E devices is available at the Texas
Instruments website
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
1
1
2
R68
4.7 kΩ
0.1 W
5%
2
GND
Figure 1-27: GPIO DIP Switch
Net Name
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
[Ref 26].
www.xilinx.com
SW12
1
2
3
4
1
R69 R71
SDA02H1SBD
4.7 kΩ 4.7 kΩ
0.1 W 0.1 W
5% 5%
1
2
R70
4.7 kΩ
0.1 W
5%
2
UG954_c1_27_041113
I/O Standard DIP Switch SW12 Pin
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
Feature Descriptions
VADJ
8
7
6
5
1
2
3
4
[Ref 35].
60
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