Xilinx VCU110 User Manual page 13

Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
2, and 3 respectively as shown in
selecting the JTAG configuration mode.
Table 1-2: VCU110 Board FPGA Configuration Modes
Configuration
Mode
Master SPI
JTAG
For full details on configuring the FPGA, see UltraScale Architecture Configuration User
Guide (UG570)
X-Ref Target - Figure 1-3
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Table 1-2. The mode switches M2, M1, and M0 are on SW16 positions 1,
Figure
SW16 DIP Switch
Bus Width
Settings (M[2:0])
001
101
[Ref 2].
Figure 1-3: SW16 Default Settings
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Chapter 1: VCU110 Evaluation Board Features
1-3. The FPGA default mode setting M[2:0] = 101,
CCLK Direction
x1, x2, x4 Output
x1 Not applicable
1 2 3
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