Jitter-Attenuating Clock Multipliers - Xilinx VCU110 User Manual

Jitter-Attenuating Clock Multipliers

[Figure 1-2, callout 12, 13 and 14]
The VCU110 board hosts three Silicon Labs SI5328C jitter-attenuating clock multipliers
(U57, U181, and U179) on the back of the board.
The SI5328C U57 HMC clock multiplier is used to generate the multiple clock frequencies
required to drive the U160 HMC device and FPGA MGTH interface.
The U57 jitter attenuated clock multiplier circuit is shown in
X-Ref Target - Figure 1-10
114.285MHZ
HMC_SI5328_XTAL_XA
1 3 HMC_SI5328_XTAL_XB
XA XB
2 4
GND1 GND2
X5 20PPM
GND
HMC_SI5328_VCC
C294 C27 C26
1 1 1
1UF 0.1UF 0.1UF
2 25V 2 25V 2 25V
X5R
GND
SI5328_INT_ALM
SI5328_RST
The VCU110 board second Silicon Labs SI5328C jitter attenuator U179 is on the back side of
the board. FPGA U1 user logic can implement a clock recovery circuit and then output this
clock to a differential I/O pair on I/O bank 128 (CFP4_REC_CLOCK2_C_P, U1 pin V34 and
CFP4_REC_CLOCK2_C_N, U1 pin V35) for jitter attenuation. The jitter attenuated clock
(CFP4_SI5328_OUT1_P (U179 pin 28) and CFP4_SI5328_OUT1_N (U179 pin 29)) are then
routed as a reference clock to GTY Quads 125, 127, 128 and 131 REFCLK0 clock inputs as
detailed in the
The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock
recovery from a user-supplied CFP4 module and use the jitter attenuated recovered clock to
drive the reference clock inputs of a GTY transceiver.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
HMC_SI5328_VCC
FERRITE-220
L31
SI5328C-C-GM
5 2 NC
VDD1 NC1
10 9 NC
VDD2 NC2
32 14 NC
VDD3 NC3
30 NC
NC4
6 33 NC
XA NC5
7
XB
NC 16 29 HMC_SI5328_OUT1_N
CKIN1_P CKOUT1_N
NC 17 28 HMC_SI5328_OUT1_P
CKIN1_N CKOUT1_P
NC 12 35
CKIN2_P CKOUT2_P
NC 13 34
CKIN2_N CKOUT2_N
HMC_SI5328_VCC
36
CMODE
3 27 NC
INT_C1B SDI
NC 4 23
C2B SDA_SDO
NC 11 22
RATE0 SCL
NC 15 24
RATE1 A0
NC 18 25
LOL A1
NC 19 26
NC6 A2_SS
NC 20
NC7
1 8
RST_B GND1
21 31
CS_CA GND2
1
U57 QFN36_6X6MM
R21
2
4.70K
1/16W
1%
GND
GND
Figure 1-10: HMC Jitter-Attenuating Clock Multiplier
GTY Transceivers section.
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
UTIL_3V3
C500
1
10UF
2 6.3V
X6S
GND
HMC_SI5328_OUT1_C_N
HMC_SI5328_OUT1_C_P
UTIL_3V3
HMC_SI5328_OUT2_P 1
HMC_SI5328_OUT2_N
2
1%
2
1/10W
HMC_SI5328_SDA
100
GND
HMC_SI5328_SCL
R1230 SI53340-B-GM
1
6
CLK0_P
7
CLK0_N
NC 3
CLK1_P
NC 4
CLK1_N
2
CLK_SEL
R1193
1
4.70K
U165
1/16W
2 1%
GND
GND
Figure 1-10.
C1626
1UF
25V
X5R
HMC_SI5328_OUT2_BUF1_C_P
HMC_SI5328_OUT2_BUF1_C_N
9 HMC_SI5328_OUT2_BUF1_P
Q0_P
10 HMC_SI5328_OUT2_BUF1_N
Q0_N
11 HMC_SI5328_OUT2_BUF2_P
Q1_P
12 HMC_SI5328_OUT2_BUF2_N
Q1_N
13 NC HMC_SI5328_OUT2_BUF2_C_P
Q2_P
14 NC
Q2_N
15 NC HMC_SI5328_OUT2_BUF2_C_N
Q3_P
16 NC
Q3_N
QFN16_SI_3X3MM
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